Historically, EBL (Electron Beam Lithography) has been utilized in the laboratory for R&D and as the tool of choice to provide the best possible accuracy and precision in the fabrication of photo masks (the master “negative” image plates used to print circuit patterns on a semiconductor wafer). Billions of complex geometric circuit patterns and device structures comprising a state of the art computer chip are designed, rendered and stored on powerful computer systems. To fabricate a photomask, the stored geometric circuit data is downloaded to an electron beam lithography system which precisely “writes” the patterns on a blank photomask coated with a special ebeam resist (which is the film on which the master circuit image is printed). After processing, the photomask becomes the photo negative utilized to repetitively print the circuit on silicon wafers moving through the production line (a process called step and repeat (the optical lithography machines are often referred to as “steppers”). This traditional technique is currently utilized to produce mask sets for state of the art lithography steppers inclusive of 193i HVM and pilot line 13.5nm EUV lithography. “Mask sets” can cost millions of dollars to produce as computational lithography corrections and computer rendering of the images are cost intensive and must produce perfectly written EBL masters. Each computer chip can have as many as fifty or more mask levels comprising the many layers in its circuit design, with each mask level taking approximately a day to produce. It is estimated that the cost of a mask set for the 20nm node will approximate $10 million considering the design and render time on powerful computers.
In addition to writing photo masks, semiconductor design engineers recognize that EBL systems can write the same patterns directly to a silicon wafer with electron beams negating the necessity of the photo masks but incurring costly write time for each wafer. Because DWEB (Direct Write Electron Beam) lithography has historically cost more than printing wafers with photomasks, its production use has been limited to very specialized high value semiconductor products (and photo masks).
Fast forward 2013. Recent advances in computing power, data storage density and computational lithography techniques are closing the cost differential between DWEB manufacturing and 193i photomask/EUV HVM. With mask fabrication costs soaring and EUV steppers priced at $125 million, the cost delta for selected applications could continue to close as EBL begins to compete with rule based mask design and wafer fabrication above the 32nm nodes, and the later implementation of Model Based Mask Data Prep (MB-MDP) for <20nm nodes. To further reduce the costs associated with lengthy electron beam write times, many propose utilizing EBL cluster tools comprised of as many as ten DWEB modules to enhance throughput. Cluster DWEB tools could be configured to match the throughput of production steppers. However, the unambiguous identification of the cost/throughput intercept point (the point when DWEB cluster and 193/EUV production throughput costs become equal) must be conclusively achieved. This will take some time as many key technologies enhancing EBL are continually evolving. In the interim, EBL provides the precision and accuracy required to produce all of the key nanometer scale lithography enablers in the semiconductor industry.
As we negotiate the path to ever smaller CDs (Critical Dimensions) it's important to note:
- EBL has been historically used to fabricate traditional optical lithography masks, 193i masks, EUV masks, NIL (Nano Imprint Lithography) molds, and enables maskless DWEB (Direct Write Electron Beam) fabrication of wafers.
- EUV has better DOF (Depth of Field) than 193i (see recent ASML data page 9).
- EBL has better DOF than EUV (and 193i).
- With better DOF, resolution and electron beam spot size control, maskless EBL could be better suited for highly resolved 20nm and <14 nm lithography.
Interestingly, this month on May 9, Ushio announced it will sell its EUV service business to ASML and discontinue further R&D on EUV source technology. (News source: Chip and Dips, Japan) Ushio's subsidiary Xtreme Technologies was competing with Cymer for EUV source business with ASML. In a vote of confidence and expediency ASML recently purchased Cymer to secure timely delivery of EUV source technology. Thirty of the Ushio staff in Germany will be assimilated by ASML in order to support its on going operations there.
The eBeam Initiative was organized in 2009 to facilitate a cooperative forum for discussion of critical issues confronting both EBL and the larger optical photomask design community. Aki Fujimura is the CEO of D2S, Inc. and also serves as the managing company sponsor of the eBeam Initiative. Comprised of over 43 member companies and advisers, the eBeam Initiative membership cooperatively collaborates on research efforts in the areas of advanced mask design, computational lithography and related semiconductor process knowledge. One of the group's projects, Model Based Mask Data Prep (MB-MDP) holds great promise for resolving many mask quality issues. The introduction of computational lithography techniques for error correction of optical distortions on masks (called Model Based Mask Fabrication) for 193i and EUV process nodes can incur significant additional analysis, write time and expense. Currently, accurate reproduction of < 32nm nanometer scale CDs for 193i and EUV often requires the implementation of OPC (Optical Proximity Correction). Ideally, the mask pattern transferred to the wafer during photo exposure should perfectly replicate the mask image. Often times patterns printed on the wafer are distorted due to stepper lens aberrations, phase distortions, diffraction related blurring and under exposure. Computational analysis of the printed distortions, stepper optics and dose parameters can yield modified mask patterns which will print optically corrected images on a silicon wafer. Although there are no optics associated with EBL, similar proximity effect distortions can appear on printed wafers after fabrication with electron beams. Secondary electron emissions created near the impinging electron beam's intended write area can expose adjacent areas on the wafer creating unwanted pattern distortions. Variations of a circuit pattern's geometry and density can result in LER, poor CDU and shot noise. For further reference: Naoya Hayashi of Dai Nippon Printing Co., Ltd recently discussed Computational Lithography Requirements & Challenges for Mask Making.
Shot noise is a phenomenon common to both EUV and EBL (for similar reasons). A low EUV photon count can contribute to optical stepper dose control issues resulting in LER (Line Edge Roughness), poor contact hole resolution, and reduction in throughput. Current EUV power output levels are insufficient and contribute to this problem. In contrast, EBL technology provides the ability to control beam current and energy over a broad range eliminating any analogous concerns with EUV source power output. As an example, Multibeam's ebeam source energy level is adjustable from 5-50KeV. In spite of this inherent advantage, it's possible that for any given chip, an electron beam with a specific process optimized energy might still under or over dose a device and surrounding structures which can have wide ranging variations in size and geometric complexities. Research continues to minimize shot noise issues for both EUV and EBL technologies.
Design for eBeam Mask Methodology (DFeB)
The eBeam Initiative has embarked on a program called the DFeB Road map (Design For eBeam see road map page 7), an industry strategy aimed at the optimization of mask fabrication techniques for scaling <20nm lithography, encompassing OPC (Optical Proximity Correction) for optical lithography, and Proximity Effect mitigation for EBL. Computational lithography techniques can be utilized to resolve complex mask error issues by implementing Model Based Mask Data Prep (MB-MDP). Analysis of OPC and/or eBeam proximity effect error data can be utilized to create software corrected mask patterns comprised of overlapping eBeam shots, circles and other optimized geometric shapes. Additional thermal analysis of overlapping shots and checks on dose accuracy can provide an enhanced data set enabling a double simulation of mask fabrication and performance for more accurate analysis and prediction of wafer quality.
The Design for eBeam Mask methodology (DFeB) can help resolve many issues inclusive of shot noise and uniformity concerns. Ryan Pearman discusses elements of computational lithography and how as a component of the DFeB strategy it can enable the segmentation and independent management of critical device patterns, structures and exposure dose on a chip. EBL mask quality can also be enhanced utilizing VSB (Variable Shaped Beam for specific tasks) to increase resolution and write accuracy, enabling the creation of specialized structures and overlapping patterns. Model Based Mask Data Prep (MB-MDP) can be implemented so that discrete structures and patterns can be addressed individually in computer memory such that each can be assigned specific shot tasking with unique eBeam energies providing control of dose margin. Called Shot or Dose Modulation, this is a new technique of assigning a unique electron beam energy and current to a specific pattern(s) or geometry stored in memory. This can enhance eBeam dose control accuracy over a chip (and wafer) potentially improving LER and minimizing shot noise typically encountered with contact holes and complex geometries. Conventional MPC can not address these problems.
While Model Based Mask Data Prep (MB-MDP) holds great promise for resolving many mask quality issues, it could further complicate Tennant's Law which observes that EBL throughput drops dramatically as geometries get smaller and resolution improves. The time required to write specific, model based process enhancing parameters for a single chip (such as proximity correction, overlapping patterns, shot count assignments and dose modulation) can probably be minimized by efficiently writing, compiling and compressing the program code as exemplified by recent efforts at Nuflare. It seems we might require a Tennant's Law Compensator (TLC). To recover CPU time lost to MB-MDP, more powerful computers and network throughput will be required. Should optimized DFeB mask designs be compiled for maskless EBL production, other major concerns in implementing cluster tools are the enormous data transfer rates and storage capacity required to replicate a large library of pattern layers. A reference document provided by Multibeam indicated that 2D lithography requirements for a single process layer currently approximates ten terabytes. EBL write speeds can reach several gigabytes per second with large cluster system data flow speeds at terabytes per second. Admittedly this represents a challenge. Perhaps there are answers at hand.
“Recently I received email communication from John S. Petersen, principal of his company, Periodic Structures/Petersen Advanced Lithography and SPIE Fellow. John has been following my blog articles on lithography and we began an email discussion of EBL data throughput issues. John categorized his work as “fringe research” indicating he was collaborating with another company to provide a 13Tb/Sec data path for eBeam lithography. John commented, “Our data path goal achieves the desired ideal in that with it we could attain the same throughput of an HVM EUV tool but there is no eBeam tool yet capable of using the pipe.” John's other “fringe research” of interest includes 2-color STED (STimulated Emission-Depletion) lithography for sub-11 nm imaging in HVM and computational microscopy. In response my comment was, “Interestingly the fringe is becoming more common place as research such as yours finds its way into manufacturing.” I've obtained permission from John Petersen to include mention of his work in this article. John advises that both of his development efforts are gated by the focus on EUV that pushes them to the fringe. Those interested in John's work may contact him at his email address, firstname.lastname@example.org.
NVIDIA recently introduced the Kepler K10 Accelerator card for PCs which is capable of Peak Single Precision floating point performance of 4.58 teraflops and Peak Double Precision floating point performance of 0.19 Teraflops with 8GB of GDDR5 memory. Up to four of the accelerator cards can be installed in parallel to achieve 18.32 Teraflops single and 0.76 Teraflops Peak Double precision calculations utilizing 32GB of memory. Clusters of these systems on a network near the fab could provide the CPU power required for MB-MDP mask enhancement support. I have to admit I was geeked and curious about the K10's price and Googled to discover that the NVIDIA K10 Accelerator card is available at Amazon.com for $2,750 (I didn't buy one). A small Windows 7 based desk top super computer is now a reality. I suspect than when CPU resource is addressed strategically the larger fab data throughput concern is a non-issue for companies such as Intel and the large foundries.
Production Throughput of Cluster EBL
EBL cluster systems could have inherent advantages in over all efficiency possibly offsetting Tennant's Law. Assuming an EBL cluster is sized to match stepper throughput, it's possible that during partial maintenance (the cluster runs at 50% throughput while half of the modules are serviced) Tennant's Law could be off set as a stepper with the same throughput would cease production completely while being serviced.
Mask Error Enhancement Function (MEEF)
MEEF (Mask Error Enhancement Function) is a measure of optical mask quality illustrating the difference between a mask's master image and the corresponding fidelity of its printed image. Images are not always replicated precisely when printed as optical effects can cause pattern feature bias issues. Smaller features are prone to larger bias errors while large features exhibit smaller errors. These errors can be magnified when changing the stepper image bias. Plotting the linearity of these differences can be challenging when optimizing mask fabrication. MEEF data and derived corrective techniques have traditionally been the domain of optical mask quality control. Recent DFeB (Design for eBeam) initiatives reflect the fact that eBeam is maskless lithography requiring similar techniques used for analysis of printed wafer quality. Anthony Adamov explains the introduction of eMEEF which similarly samples image data to provide corrective guidance. eMEEF data can be derived and analyzed from two identical images written at different beam energies. As optimized eBeam image quality is typically better than that achieved with an optical mask, eMEEF data looks better than its comparative optical (MEEF) counterpart.
Particulate Reduction and Management
It would seem that EBL systems might be inherently cleaner than a Laser/Sn EUV stepper from a particulate control perspective. Laser/Sn based EUV sources generate large numbers of tin particulates necessitating hardware shielding, or magnetic field mitigation techniques to protect optics and critical surface areas near the source and wafer stage. As there is no mask transfer activity or pellicle handling associated with EBL, remaining concerns might include residual carbon particles accumulated on eBeam optics or more traditional “particle added” wafer handling issues. Particulate contamination of an EUV mask is a critical concern and can compromise weeks of work and millions of dollars invested in mask fabrication. A recent SPIE News Room article features a paper, Repairing photomasks by nanomachining by Gregory McIntyre, Emily Gallaghar, Mark Lawliss, Tod Robinson, Michael Archuletta and Ron Bozak. The paper illustrates a repair technique for use on highly sensitive EUV masks. Particles can be added during mask handling and can also be intrinsic to mask blank materials. Tests conducted on a six inch EUV photomask revealed that a single 1nm tall particle created a multilayer defect which rendered the mask useless. In an ingenious repair effort, the authors of the paper employed the use of an AFM (Atomic Force Microscope) to nanomachine and repair the site of the 1nm particle induced defect. The operation was a success and illustrates the high costs associated with mask management for 13.5nm EUV. As there is no mask or pellicle hardware associated with EBL, resulting longer term mask cost and salvage/repair savings could provide an additional cost offset in favor of cluster EBL for HVM.
David K. Lam, Ph.D., Founder of Lam Research, CEO and Chairman of Multibeam Comments on Multibeam's Market Entry Strategy and System Design Features:
“Yan Borodovsky, Ph.D., Intel’s lithography guru, envisioned e-beam lithography working as a cost-efficient complement to optical lithography during a presentation he made in 2010. Supporting the practicality of his vision was the shift that major IC manufacturers were making from using irregular two-directional (2D) patterning to regular “gridded” unidirectional (1D) patterning. Borodovsky’s vision has given rise to Complementary E-Beam Lithography (CEBL), a new class of semiconductor production equipment.”
There has been much past and present speculation of where Electron Beam Lithography might play a role in the wafer fab as either a complementary tool or a competitive challenge to 193i and future EUV HVM. In preparing this article I thought it important to include discussion with a real, viable semiconductor equipment manufacturer positioned for HVM market entry with a well defined cluster EBL strategy. Having founded Lam Research, David K. Lam, P.h.D. has again demonstrated his industry insight in positioning Multibeam for timely entry to the nanometer scale semiconductor lithography HVM environment. Communicating with Dr. Lam via email I forwarded him a list of questions in an effort to interrogatively summarize Multibeam's approach to the current and future semiconductor market. The questions are mine with responses provided by Dr. Lam in a recent email exchange:
Thomas D. Jay, Semiconductor Industry Consultant
“What prompted the semiconductor industry's transition from 2D to 1D patterning?”
David K. Lam, P.h.D., Chairman and CEO, Multibeam
“By shifting from an irregular 2D to a “gridded” 1D design layout style, leading chip makers are now defining circuit functions with simpler unidirectional “lines” and “cuts” – which enables device scaling beyond what is possible using conventional 2D random layout and paves the way for complementary lithography solutions. Multibeam’s Complementary E-Beam Lithography (CEBL) offers a compelling complement to both existing 193i and EUV lithography as it can “cut” lines at critical layers and do so at relaxed tolerances without the need for costly masks.”
Thomas D. Jay
“What specific criteria was utilized to define Multibeam's anticipated target market for 1D CEBL patterning?”
David K. Lam, P.h.D.
“The use of “Gridded” 1D Layout Style by leading chip makers started in 2007. Since then, IC designers have increasingly adopted this unidirectional “gridded” 1D layout style to overcome a major roadblock to scaling and manufacturing advanced logic devices. Patterning lines-and-cuts involves printing and cutting gratings. While 193i remains excellent for printing the lines, cutting the lines is a different matter. As nodes advance, optical cutting requires complex optical proximity correction (OPC), multiple patterning, and expensive cut masks. CEBL promises a compelling cost-efficient lithography option. Multibeam expects its CEBL to be used by both IDMs and Foundries to reduce optical lithography costs in processing both complex logic and memory chips at high volumes. Moreover, when EUV becomes available and is used to pattern below 13.5nm, there will be severe OPC and other resolution problems, which CEBL can help resolve by performing line cutting and eliminating costly multi-patterning at critical layers. Optical lithography line-cutting is very expensive due to the soaring cost of mask sets. Accordingly, CEBL offers a compelling alternative to “cut” the lines with no masks at certain critical layers. Thus CEBL can work hand-in-hand with optical lithography, which would continue to reliably print the lines to demanding critical dimensions and line edge roughness specifications.”
Thomas D. Jay
“Given the high costs of data storage, the computational overhead associated with EBL and Model Based Mask Data Prep (MB-MDP), could the migration to CEBL 1D HVM challenge Tennant's Law and result in higher manufacturing costs?”
David K. Lam, P.h.D.
“The Shift to “Gridded” 1D Layout Style combined with Multibeam's multi-column approach streamlines the storage and transfer rate of data patterns; as much as three orders of magnitude less pattern data and lower transfer rate are required. Multibeam leverages the 1D-layout trend in developing its multi-column CEBL system to pattern line-cuts and complement optical line-printing. 1D + Optical + CEBL enable advanced logic devices to be fabricated cost-efficiently in HVM environments.”
Thomas D. Jay
“Multibeam has opted to enter the wafer fab market with 300mm wafer tooling. Are there plans to expand to 450mm?”
David K. Lam, P.h.D.
“Multibeam’s multi column architecture can be easily scaled to pattern 450mm wafers with no throughput penalty. Moreover, multiple modules can be integrated into a “cluster tool” to boost throughput as each module writes on a separate wafer, reaching a combined throughput level compatible with high-volume manufacturing (HVM) production flow. The multi-level redundancy of Multibeam’s proprietary multi-column architecture combined with today’s high-reliability thermal field emitter source assure an uptime, MTBF, and equipment utilization comparable to process equipment used in HVM environments.”
Thomas D. Jay
“Could you describe Multibeam's EBL Conceptual Design and Function?”
David K. Lam, P.h.D.
“Embodying four generations of development, Multibeam’s proprietary e-beam technology deploys a scalable multi-column array of miniature columns. Each column is controlled electrostatically with no magnetic field, and each is powered by a Schottky thermal field emitter. Adjustable in beam energy from 5 to 50keV, each column contains a single beam; there is no beam splitting. Multibeam’s unique architecture enables some 100 e-beam columns to be arrayed in a single module to print a 300mm wafer. Each mini-column is about the size of a marking pen and each array matches the size of a wafer. The columns in an array write independently and in parallel to achieve a throughput of 5 wafers per hour.
Significantly, the absence of magnetic fields (and magnetic hysteresis) enables the e-beam in the column to be deflected at high speeds for blanking, positioning, shaping, and focusing. Multibeam optimizes its mini-columns at beam energies below 30keV, compared to other conventional EBDW systems running at 50-150keV. Multibeam has developed companion technologies to further protect sensitive high-performance SoCs from any electron-induced damage while making the column array robust and lower-cost.
Vector scanning by each individual beam is another crucial capability and key differentiation of the Multibeam approach. Multibeam’s vector-scanning technology enables each e-beam in the array to be individually deflected to where there is a pattern to write, efficiently skipping over wafer areas where there is no patterning required.”
Thomas D. Jay
“There is much debate surrounding EUV resist performance issues. What unique concerns might there be for ebeam resist performance in a demanding nanometer scale HVM environment?”
David K. Lam, P.h.D.
“Multibeam’s e-beam technology uses commercial e-beam resists —including those that are currently used in mask writers. Widely available, these resists have been refined over three decades. In addition, carbon contamination can be cleaned with well-established techniques used in the Scanning Electron Microscope industry. EBDW does not involve tin, so there is no contamination associated with this metal as in EUV.”
Thomas D. Jay
“Have you any closing thoughts on Multibeam's confident market entry and future positioning?”
David K. Lam, P.h.D.
"Overcoming the wavelength limitations of optical lithography to produce ever smaller transistors is becoming very challenging. It’s no longer just a technical challenge…it is now a huge economic hurdle. While there is hope that EUV (soft X-ray) lithography will be the “next generation” disruptive solution, protracted delays in coming to market combined with EUV’s extraordinary high cost and a requirement for a vastly different infrastructure (e.g. new resists, new masks, etc) has opened the door for complementary solutions to play a cost-efficient role in reducing lithography costs.”
Dr. Lam comments that in addition to the technical challenges of EUV there are also economic challenges. So to with eBeam. However, I believe there is a compelling case for the implementation of an EBL HVM strategy. EBL will accelerate lithography enabling process evolution via Model Based Mask Data Prep (MB-MDP) along with other cost saving and process advantages to the HVM wafer fab.
I'd like to thank Dr. David Lam, Chairman, CEO, and Tom Rigoli, VP of Marketing at Multibeam Corporation for graciously responding to my inquiries, providing back ground information and insight on eBeam lithography and Multibeam.
Thomas D. Jay
Semiconductor Industry Consultant
PDF Download Link
I'd like to thank the following semiconductor industry professionals and Lawrence Berkeley National Laboratory SEMI affiliates for responding to my research inquiries in preparing this article on eBeam lithography.
David Lam, Ph.D., Founder of Lam Research, Chairman & CEO, Multibeam Corporation, Chairman, David Lam Group
Tom Rigoli, Vice President, Multibeam Corporation
Patrick Naulleau, Ph.D., Director, CXRO, Lawrence Berkeley National Laboratory
Kenneth Goldberg, Ph.D., Deputy Director, CXRO, Lawrence Berkeley National Laboratory
Chris Mack, Ph.D., Litho Guru, and Gentleman Scientist, (with F.M. Schellenberg, MEEF in Theory and Practice)
John Petersen, Principal, Periodic Structures/Petersen Advanced Lithography & SPIE Fellow
Referenced Presentations and Technical Papers
Yan Borodovsky, Ph.D., Director of Advanced Lithography, Senior Intel Fellow, Intel Corporation, The various paths to next-generation lithography, SPIE TV, You Tube
Naoya Hayashi, Dai Nippon Printing Co., Ltd, Computational Lithography Requirements & Challenges for Mask Making
Repairing photomasks by nanomachining by Gregory McIntyre, Emily Gallaghar, Mark Lawliss, Tod Robinson, Michael Archuletta and Ron Bozak, SPIE News Room
Anthony Adamov, D2S, Introduction to eMEEF, You Tube
Ryan Pearman, D2S, Discussion Computational Lithography, You Tube
The Story Behind My Interview With Dr. David K. Lam