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Wednesday, April 10, 2013

Direct Write E-beam Lithography; Complementary Technology in the Fab


On April 7, 2013 Yehiel Gotkis commented on my recent March 20, report on SPIE Activities (scroll down to my prior post) which spoke to developments in EUV lithography and related process issues.  Yehiel questioned why my comments did not include discussion of Direct Write E-beam Lithography.  Burn Lin of TSMC recently presented a status update on DWEB lithography at SPIE Advanced Lithography IV which prompts further discussion of this complementary lithographic technology.  My response to Yehiel's comments follow:

Thank you for your observations on e-beam lithography.  In my opinion direct write e-beam technology continues to demonstrate its value as an important component in the mix of lithography strategies used in both current and future semiconductor production.  In addition to my recent blog comments on EUV, I made a brief reference to direct imprint, multiple e-beam and Directed Self Assembly (DSA) as supplemental alternatives to EUV lithography.  My omission of commentary on e-beam technology was not intended to minimize its importance or viability in the semiconductor manufacturing market place.  If there is limited success with the further increase of EUV source output power the extended dose/exposure times will enhance the competitive viability of e-beam lithography for HVM (High Volume Manufacturing).

As the semiconductor market evolves there will be niche markets for application specific lithography technologies which are best able to address process problems unique to newly emerging segments of the semiconductor industry.  Currently, industry interest is focused on resolving EUV lithography HVM issues as evidenced by recent investments in ASML by Intel, TSMC and Samsung.  Is direct write e-beam an HVM alternative to EUV or 193 nm lithography?  For High Volume Manufacturing of RAM memory, many MPUs and other high volume commodity products the answer is probably no, not at this time, but events change quickly.  This observation in no way disqualifies e-beam from other market segments where it has real value.  In the 1980s IBM had a production line called QTAT (I'm sure the QTAT example has been cited many times).  This was a Quick Turn Around Time direct write e-beam production line which supplemented the traditional optical lithography line.  As explained to me by IBM years ago, one of the intended purposes of QTAT was to enable the IBM sales and marketing team to respond quickly to customer orders which were time sensitive.  Traditional sales activity hand off to the wafer fab involves the strategic scheduling of fab assets to accommodate work flow determined by the mix of products in the factory. Often times this scenario represented multiple customers with specific, time sensitive delivery requirements.  In most cases this work flow was efficiently scheduled on the optical lithography line where production costs were minimized.  However, on occasion the fab would receive a time sensitive order which could not be easily integrated into the mix scheduled for optical production.  These orders were sometimes routed through QTAT.  In addition to the many standard photo mask sets in place at the IBM wafer fab, much of the product line was also replicated on the direct write e-beam system computers.  When there was a resource conflict for use of the optical lithography line, the work flow could be diverted to the e-beam line.  It was a simple matter to down load the e-beam lithography patterns with out concern for the time consuming loading and qualifying mask sets.  It's probable that in most situations this was more cost and time efficient than work flow disruption of the optical line or loosing time sensitive orders to competition.

In today's foundry environment, direct write e-beam can provide a similar quick turn around back up capability on the production line.  In addition to the significant evolution of e-beam lithography capabilities over the years recent renewed interest in complementary lithography support might also be reflective of the historic value of the QTAT concept.  The ability to develop new products without concern for mask design/fabrication and optical lithography hardware can be very influential as the cost of nanometer scale production escalates.  

It is rumored that direct imprint lithography systems are currently in use at a major flash memory manufacturer where complex, high cost products are being produced.  In the absence of HVM EUV and given the added costs and complexities of 193 nm double patterning, direct imprint lithography can also become a contender for many niche applications.

Next generation nanometer scale lithography technology continues to evolve.  Mapper, KLA-Tencor, JEOL, Multibeam, 
PARAM, and Vistec are all engaged in research which pushes the envelope in both development labs and production fabs.  Many industry actions and decisions will be keyed upon successful scaling of EUV power output, mask and resist issues.  With regard to e-beam direct write systems, it's interesting to note that the full complement of current MEMS technology is being leveraged to create the electrostatic lens systems that enable some multiple e-beam lithography systems with their precision. A technology shake out is in progress. 

Direct write e-beam lithography has its own set of advantages and technology node issues worthy of further discussion.  I plan to report on e-beam lithography more expansively in the coming weeks.


Thomas D. Jay
Semiconductor Industry Consultant
Thomas.Dale.Jay@gmail.com
www.linkedin.com/pub/thomas-d-jay/26/aa3/499
ThomasDalejay.blogspot.com

The Technology High Ground



12 comments :

  1. Tom, it came out more than 4096 characters, so, I am splitting it in 3 section.

    Section #1
    The discussion I initiated at Linked In for quite a while ago titled:" Direct Write E-Beam Liitho- is it a Reality or a Wishful Dream? Well, maybe a greatly expensive dream..." is still running.
    You suggested I share my concerns associated with DW EBL for HVM, and specifically with the Digital Pattern Generator, or DPG. Indeed DP is an absolutely new conceptual element, which does not appear in the conventional EBL configuration. The litho community and engineering does not have any prior art knowledge and experience allowing to realistically foreseeing the DPG specific effects and how these effects may influence the e-beam writing.
    In the P(seudo) M(ulti) B(eam) DW EBL concept, a pixelated DPG device is imbedded between the emitter and the wafer. The DPG splits the incoming electron beam into a multiplicity of fine beamlets each of them to be independently manipulated by the pixel charge. Each pixel is configured as a multi-electrode well, electron reflection efficiency of which is extremely sensitive to the geometry of the within-well electrical field, which in its turn is strongly dependent on the well surface state, which in its turn is extremely sensitive to surface contamination, charging, modification, re-structuring, thermal conditions and a number of other factors, being conditions-, time- and environment-dependent. It rises intense concerns about the DPG conceptual functionality. For anybody competent in advanced technology development it would not make any sense to start building a complex expensive machine, even a simplified prototype, without clearing the feasibility of GO-NO GO gaps.
    More than 5 years passed since the KLA-REBL program have started in full volume and from the very early stages the team was, and still mostly is focused on designing and building columns, magnetic levitating stages, and a variety of other construction activities, whatsoever, attempting to make a litho machine. Unfortunately, no proper attention was attributed to the DPG design, its fabrication and especially testing its conceptual functionality. I believe even by now they at KLA-REBL do not have a clue if the required DPG functional capabilities are in principle feasible.
    It is hard to find a rational explanation why REBL leadership decided to focus on building expensive HW without getting clear answers to the fundamental feasibility-controlling questions. I guess, all the conceptual feasibility testing costs would not exceed $1-2M, and these MUST BE DONE tests had to be carried out first thing in the morning in the very early stages of the project. Because if the heart of the concept, the DPG functioning is not feasible, spending $100Ms on building monstrous columns, stages, developing supporting SW etc. etc. is waste of $$ and an indication of lack of adequate vision.
    As you may know, I was in the REBL nucleation team since its very establishment. I know well the REBL conceptual formula and associated Pros and Cons. At this point, given the state of the art of the advanced science, and engineering, the probability to resolve quite a number of heavy NO GO problems, is, to my opinion, infinitely close to zero, requiring not just improved scientific and technical understanding, but some requires some "wishful" science. The DPG, not the column, and not the electron source, and not the stage, and not the resist, and not the data transfer SW, the DPG is the central element, the heart of the PMB DW EBL concept. And the concentrate of unknowns and major feasibility doubts. Pay attention, Burn Lin avoided any comments about the problems associated with DPG functioning.
    As a chemist, and a physicist, and advanced technologist, being tightly involved in the REBL DW EBL program for quite a prolonged time, I believe I understand the situation there much better than many other external analysts and I think there is no solution there.

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  2. Section #2
    Very recently, REBL guys, actually this is just Mark McCord, took the bravery to talk openly about some conceptual problems requiring solutions to make the DW PMB EBL working. "There are several technical areas where research advances would improve the capability not just for REBL but potentially for other electron beam lithography approaches as well. ….Surface science studies on mitigating charge buildup and carbon contamination on optical components exposed to the electron beam would improve beam control and system performance. Novel cathode technologies for high current sources with low energy spread would improve illumination performance, dose control, and beam blur. Examples of how these areas impact electron beam lithography performance will be presented and possible research directions will be proposed." Abstract: REBL High Throughput Lithography Program –Overview and Key Areas for Future Research http://www.src.org/calendar/e003804/mccord-abstract/
    In the REBL previous publications the charging problem was reported as being resolved, however, as per Mark McCord, it still requires "surface science studies on mitigating" it.
    As far as carbon contamination problem is concerned - it is one of the oldest age-long problem, which was attacked by CD SEM professionals so many times, and was actually never resolved, because it is intrinsically associated with e-impact induced deposition of the background organics. What does it mean for REBL? Carbonization affects the pixel electrical and, as a result, e-reflection performance, and it takes seconds, in the best case minutes for carbonization to show up on the wafer surface in CD SEM machine. It means that the hope the DPG can demonstrate stable performance work for a reasonable amount of time is just a fantasy, and it does not require to be a rocket scientist to realize it.
    Another quite fundamental problem of high throughput EBL is associated with the huge amount of heat generated both by the integrated CMOS+DPG device, which is well thermally insulated, and by the writing beam at the wafer.
    From the Mark McCord's abstract: "REBL (Reflective Electron Beam Lithography) is a program for the development of a novel approach for high-throughput maskless lithography. The program at KLA-Tencor is funded under the DARPA Maskless Nanowriter Program. A DPG chip containing over 1 million reflective pixels that can be individually turned on or off is used to project an electron beam pattern onto the wafer. The DARPA program is targeting 5 to 7 wafers per hour at the 45 nm node, and KLA-Tencor is working on improvements to both increase the throughput as well as extend the system to the 2x nm node and beyond."
    It sounds as even this target is already achieved, and a corresponding lithography machine exists ready to process wafers at a trusted foundry, and KLA-Tencor/REBL is working on advanced improvements now. Well, in reality nothing even close to a litho machine, even a primitive prototype, was ever made.
    The best REBL-published achievement in resolution, I believe exposed in a static mode, is 100 nm lines, an achievement which could be qualified as a great one... if we were at the end of the previous Millennium. Today, in 2013 it sounds like a Stone Age achievement.
    The set of basic research projects, Mark McCord proposes to discuss in his SRC presentation would sound absolutely great if REBL was in the program early stages. Coming up with such a “great” plan now, after more than 5 years of spending $Ms on columns and stages construction sounds a little bit belatedly and in a sense funny.

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  3. Section 3
    These are the matters associated with the DPG. However, to my opinion, the EBL #1 trouble is coming not from how to make a functional DPG, but from the basic Physics, namely, from the fact that beam electrons penetrate into the device space potentially causing significant device functionality damage. Chemical transformations are inevitably induced by the 20-100 eV secondary electrons yielding electrical response transformations deadly for the device performance. This intrinsic EBL problem does not appear to be fixable, especially for advanced nodes while working with 50-100 KeV electrons.
    What worked safely in the past for the sub-micron sized devices becomes an endangering factor for the advanced nodes, especially when high throughput goal is targeted. Especially vulnerable I would expect to be the device interfaces, where e-impact induced interaction between the contacting materials could be very efficient, and by-products formed could possess extremely undesired properties, affecting the device short- (yields) and long-term (reliability) performance.

    Here is a study “CMOS degradation effects due to electron beam lithography in smart NEMS fabrication” ( http://proceedings.spiedigitallibrary.org proceeding.aspx?articleid=865721 ), and the authors’ concluding remark are:
    “The effects of electron beam lithography for patterning to the nanoscale a polysilicon layer electrically connected to the gate of an NMOS transistor are investigated... The results obtained show that a severe degradation of the transistor characteristics occurs when processing at high acceleration voltages. The degradation is observed as a threshold voltage shift and a decrease in the transconductance. This behaviour can be related to positive charge trapping in the gate oxide and generation of interface states at the SiO2-Si interface. The results suggest that the secondary radiation created by the primary electron beam is damaging the transistor characteristics and can lead to the loss of circuit performance when using electron beam lithography to fabricate nanostructures in already processed CMOS circuits.”

    And another one:
    Investigation of Reliability Degradation of Ultra-Thin Gate Oxides Irradiated under Electron-Beam Lithography Conditions http://adsabs.harvard.edu/abs/2000JaJAP..39.2181C

    “Effect of Electron-beam irradiation on the reliability of ultra-thin gate oxide has been studied under typical Electron-beam lithography conditions. A large increase of low-field excess leakage current was observed on irradiated oxides, which was found to be very similar to the electrical stress-induced leakage currents. An experimental relationship between the total Electron-beam dosage and the equivalent charge fluence, which induces the same amount of current degradation, has been established for different oxide thickness... It has also been found that Electron-beam irradiation generates much larger amount of oxide bulk traps but generates a comparable amount of interface states, compared to electrical stress."
    And a few other studies:
    Total Ionizing Dose Effects in MOS Oxides and Devices http://radhome.gsfc.nasa.gov/radhome/papers/tns03_oldham_TID.pdf
    Electron-Beam-Induced Damage in Self-Assembled Monolayers
    http://www.parikh.ucdavis.edu/pages/publications/Publications_pdf/JPC_1996_Kannan_ebeam.pdf
    Electron-beam irradiation-induced gate oxide degradation http://jap.aip.org/resource/1/japiau/v88/i11/p6731_s1?isAuthorized=no

    These works just should not be ignored, unless somebody finds serious reasons to disqualify all their authors. Pay attention that all these studies are carried out with low throughput single beam tools. One should expect the spectrum of damage/degradation issues to widen and intensify with the high current PMB DW concepts.
    Tom, I believe I covered the main points.
    Thanks,
    Yehiel

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  4. Tom, can you elaborate your statement "significant evolution of e-beam lithography capabilities over the recent years..."? What evolution/advancement are you referring to? Is it about the Pseudo-multi-beam concept? NO ANY PRODUCTION CAPABILITIES were yet demonstrated. At least I am not aware about the actual progress. New e-beam resists - yes, better optics and emitters for resolution - yes, but production ready machines capable to process full surface of 300-450 mm wafers in reasonable time (at least 1 w per day, or maybe even 1 wafer per week) at advanced nodes (45 nm and beyond) - GREATLY PROBABLE NO.
    So, Tom ("Amicus Plato, sed magis amica veritas."), please excuse me for this harsh question, but what EBL@MANUFACTURING FLOOR advancements are you aware about? Yes, it works at University labs, in some R&D facilities patterning 1-2 1"x 1" of not really advanced node die clusters per day, but real fabrication of production wafers- I am not aware about such cases.

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  5. This comment has been removed by the author.

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  6. Tom, I introduced a couple of corrections into my previous comment and tried to delete that version, but I am not sure it worked. Please delete it if may attempt was unsuccessful


    Also, Tom, do you still believe REBL or Mapper or any other EBDW guys will join your discussion. I doubt, I do not think they have guts. They just have no real data and facts to bring to the discussion table.

    Look, Pieter Kruit, the Mapper co-founder, distanced himself from active involvement in the Mapper technical and managerial space- it indicates about something.. Mapper promised ("In 2012 Mapper will complete its Matrix pre-production platform with initially a 1 wafer per hour throughput capability and scalable to 10 wafers per hour," said Bert Jan Kampherbeek, CEO of Mapper, in a statement issued by CEA-Leti.) 13K e-beam machines shipment to LETI and TSMC did not happen.

    I just discussed with one of my friends, who is a greatly experienced litho professional, my concerns related to e-impact induced device damage and here is his response: ".. those are real concerns and corresponding experiments must be done prior to inclusion of EBDW into anyone development process". I am sure, anybody who is reasonably familiar with the e-impact induced phenomena understands the associated risks, and "corresponding experiments must be done" prior to spending $100Ms on construction of columns, guns, developing data transfer SW, designing and fabricating DP etc. Especially because the associated experiments, if properly designed, are extremely simple and inexpensive and their data are also clearly interpretable. This is what I would do to evaluate the e-impact device damage : e-irradiate a yield-tested wafer simulating the PMB conditions, and re-run the yield test to evaluate the e-impact induced yield loss. I am sure results of such an experiment would clearly vote to GO for the next step, DPG design and fabrication, or NOT TO GO. Only after this, assuming the result will be positive (NO YIELD LOSSES)it would make sense to go for conceptual DPG functionality and stability tests, most of which, BTW, do not require a fully functional DPG chip.

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  7. Tom, let me remind you about a specific feature of the photo-lithography, the PELICLE.
    Particle contamination is a problem in semiconductor manufacturing. A photomask is protected from particles by a pelicle, a thin transparent film located far enough away from the mask, so that moderate-to-small sized particles that land on the pellicle will be out of focus. The DPG,, which actually acts as e-beam patterning unit, cannot be protected in the same way as the photo-mask is. Additionally to this the particles, landing over the DPG surface are quickly charging and repelling the incoming and outgoing electrons from their desired trajectories distorting the original pattern.
    I do not see how this problem could be fixed

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  8. Tom, here is my conclusive remark (my personal opinion):

    DW EBL has very little, if any, chance to become a viable production tool because of:

    1. High risk of device damage due to e-impact induced transformation of material and, consequently, electrical properties - for both SB and PMB DW EBL
    2. Practical un-sustainability, in production reasonable time (hours), of the DPG functionality and stability, due to active surface contamination, charging, landed particulates, high energy ion bombardment, and also due to extremely high amounts of heat generated by the DPG functioning and very limited cooling options (remember, DPG is under full acceleration voltage, 50-100 KeV).

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  9. Dear Yehiel,
    Not all the EBL will use 50-100 Kev, the one of MAPPER is using 5 KV, this will have the following advantages,
    1. High througput, MAPPER is targeting a 100 wph system, thanks to the low acc. volatge and the design.
    2. This will solve/minimize the impact of the ebeam and all the consquence of it like heat or damage...

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  10. Dear Anonimus,
    You consider 5 KeV LE as an advantage... Well, here is a couple of counter arguments:

    1.To keep the resolution with 5 KeV LE it will require ultra-thin resist film, which is associated with a whole bunch of special problems (uniformity, meso-structuring, unique formulations, increased shot noise associated with much lower number of AGs etc.)
    2. The electron impact interaction (and damaging)cross section is getting to its max value at 75-100 eV interval, meaning that 5 KeV electrons could be even more device damaging than 50 - 100 KeV electrons. The scattered electrons cloud for 5 KeV electrons is located within few dozen nm below the surface exactly where the devices are located, while 50-100 KeV scattered electron cloud is located much deeper, at the depth of few microns or more...
    I believe it makes clear why 5 KeV electrons are not safer as far as device damage is concerned.
    However all other conceptual show-stopping limitations, associated with the pattern generation device are still at the Mapper's map and at the REBL map and any other PMB concept delusioned technology developer.

    This probably explains why we do not hear any sounds of fanfares neither from Mapper, nor from REBL or whoever else is pursuing this venue.

    It is unrealistic to hope that Physics and Chemistry, the basic laws of which stipulate these showstopping barriers, will for some reason decide to make the PMB guys an exclusive favor not interfere in their, Mapper, REBL etc., specific particular cases.

    Best,
    Yehiel

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  11. Well, finally REBL is terminated as lacking delivering. "Finita la commedia..."

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  12. A couple of weeks ago I decided to end up with the DW EBL discussion due to no sense to go on with it because it looked like everything that could be considered considering the PMB DW EBL for wafers was already discussed and concluded… And the most recent developments in the field proved the conclusions to be adequate.
    However, recently I ran into some stuff that convinced me to put together this note because it is not about the past state of the art of this technological concept but about its future.
    I found out that there is quite a number of theoretical works analyzing the EBL concept consistently indicating that the writing rate is reverse proportional to the resolution in power 4,
    WR ~ r^4
    Which immediately triggered in my mind the following speculation:
    1. KLA-REBL promised to switch their targeted machine specification to run 100 wph by clustering 100 columns in one parallel processing machine expecting the resolution to meet up to 10 nm. Let us see how “scientific” was their estimation
    2. Assuming they@KLA-REBL succeeded with their 45 nm column (5 wph). Just to meet 100 wph target REBL would need 20 columns. The resolution increase to 18 nm is (45/18)^4≈ 40, and to 10 nm, correspondingly, 400, which brings us to an estimation of at least 800 columns for 100 wph@18 nm and 8000 columns for 100 wph@10 nm, by far more than their self esteem of 100 columns.
    One can say that if I discovered it just now, why other PMB DW EBL guys could not also miss it. Well, I am just a chemist, so, what could be an excuse for me could not be an excuse for strategists and litho technologists leading such a important program as KLA-REBL, projecting 100 wph@10 nm with 100 columns,- just a misleading a pure wishful fantasy. Especially, not an excuse because the first work published on the r^4 matter came from Prof. Fabian Pease from the neighboring Stanford back in 2007.

    I believe the r^4 law indicates that even the true MB DW EBL future is under a big... well, a very very big question

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Your comments are welcome. I'd like to hear your thoughts and opinions. Many thanks for your readership. - Thomas D. Jay