Tuesday, August 19, 2014

The EUV Continuum - Have You Seen the Light? It is August, 2014. Semicon West has long past and from an EUV perspective not much has changed. Another year, another conference series, and still no news to report on high power EUV product offerings other than another forward looking statement from ASML anticipating >100 watt EUV power levels at Semicon West next year. Recently developed EUV resists formulated at Lawrence Berkeley's CXRO have been a bright spot in recent developments.

It would seem the past ten years have been a repeating loop in which the on-going investment in EUV technology has yet to yield results commensurate with the engineering tours de force resident at ASML and the consortium of semiconductor manufacturers who have become its major stock holders. The last major engineering enhancement credited with increasing EUV source power was the fine tuning of a pre-pulse laser, providing a few additional watts but still short of required HVM power levels. How will EUV power output be optimized to required HVM power levels? At the moment, there are no clear answers. 

The multi-billion dollar semiconductor industry that has sustained Moore's Law continues to finance research and development over a multitude of technologies which will collectively enable 7 nanometer process technology and future picometer pursuits. It is a given that major players in the semiconductor equipment industry have deep pockets with which to market capital intensive technologies while quietly developing next generation products in a less than optimal economy.  Collectively the semiconductor manufacturers and the equipment industry exhibit massive economic momentum which occasionally slows to assimilate new markets and pre-position next generation technology products. This massive economic momentum also foments evolutionary technology championed by industry visionaries. Long term investors familiar with the semiconductor market segment have become adept at reading the strategies of key industry players, drawing confidence from past performances, and the solutions to seemingly unsolvable engineering challenges to Moore's Law. Although EUV technology has yet to yield HVM performance, the sheer momentum of the industry will sustain alternate technologies as interim solutions to the EUV dilemma. ASML has maintained its leadership in the lithography markets by optimizing current 193nm lithography with multiple patterning techniques, providing half pitch resolution with sufficient precision to accommodate challenging process nodes  =<10nm. As such, ASML will continue to enjoy leadership positioning in the 193nm markets while seeking engineering solutions which will ultimately enable higher power EUV. Directed self assembly techniques (DSA), and Nano-Imprint Lithography (NIL) continue to gain acceptance and process share as these technologies mature.

In observance of the ten year EUV odyssey, we should pause to reflect on the industry and its steadfast pursuit of EUV technology despite continual reported delays and setbacks in the program. Teams of Ph.D. researchers and engineers conduct a relentless effort to improve the performance of key manufacturing systems, continually upgrading the production, precision and metrology required to produce consumer products by mass assembly on an atomic scale.  EUV technology is recognized as a key enabler to lowering production costs by providing superior nanometer scale imaging and reducing the number of cost intensive mask levels for a given product. For the past ten years we have observed incremental progress in EUV and the infrastructure required to facilitate its HVM insertion.

Over the years, the cost of R&D associated with semiconductor process development and related lithography tooling has risen dramatically. Thus far, such cost barriers have been overcome by the efficiently pooled resources of the semiconductor industry and equipment suppliers, reducing costs by sharing resources and the associated expense burden. Historically, SEMATECH has lead many successful technology initiatives bringing complex R&D programs to operational status in the wafer fab. Other groups such as the G450C have teamed to provide the capital and engineering expertise required to meet the future 450mm HVM insertion time line.

If we find ourselves disappointed with current developmental efforts in EUV, what then might we consider newsworthy?  In a July 10, 2014, IBM press release, plans were announced for the company to invest $3B over the next five years on advanced semiconductor technologies.  Historically, IBM's R&D expenditures have averaged $6 Billion annually, spread over many disciplines. The commitment of an additional $3 Billion suggests a 10% increase in IBM's R&D program over the next five years. As IBM intends to make investments critical to future semiconductor device design (and by linkage required lithography techniques), is it possible that IBM will conduct its own initiative to further the development of EUV (Extreme Ultra Violet) light source technology?  High power EUV must be proven reliable to ensure the availability of future 13.5nm lithography HVM.  On July 25, 2014, I emailed the IBM media contact referenced in the news release, seeking clarification on IBM's $3 Billion budget increase announcement. My inquiry is currently unanswered, however on July 29, 2014, Dan Corliss, IBM's EUV Lead Technologist and Program Manager for Lithography R&D, announced a recent test in which their NXE:3300B stepper had been upgraded with a 44 watt EUV light source (as measured at the intermediate focus) and had produced 637 wafer exposures in “normal production mode”. No doubt, this announcement was intended to renew enthusiasm in the EUV program and highlight IBM's participation in an on-going industry wide effort.  However, the news quickly drew skepticism and later criticism when it was learned that the NXE:3300B's actual run rate was 34 wafers per hour, inclusive of two system “process interrupts” during the 24 hour test. Two industry analysts injected further criticism pointing out the EUV energy/dosimetry was insufficient for HVM and that blank wafers were used for the test, yielding no real data for viable analysis. Suggestions were made that the reports of the test results were misrepresented and that stock holders investing in EUV semiconductor lithography were possibly being mislead.

Let's step back for a moment and consider this latest IBM test in context with historic EUV light source development. Since the inception of the EUV program at the National Ignition Facility over ten years ago, EUV power levels (as measured at the intermediate focus of lithography tools) have yet to achieve sustained >150 watt power levels required for HVM (High Volume Manufacturing).  Although there have been reports of higher output power levels approximating 100 watts, these results represent peak power levels observed for brief periods which have not been sustainable during extended operational tests. More recent EUV source shipments from ASML have demonstrated EUV power levels of 25 watts with newer upgrades enabling 40 watt capabilities as recently reported by IBM. The ten year reporting history of the EUV program reflects the power limitations imposed by conventional physics and our struggle to rewrite the rules. We've modified the rules previously with man made additions to (and harvesting of) the periodic table proving hafnium is better than none. But, in the realm of semiconductor manufacturing, a fifty percent EUV power solution is unacceptable. The recent IBM test was part of a continuing effort to evaluate the incremental improvements made to EUV source technology and should not be interpreted as a failure.

In previous blog articles I've proposed solutions to resolving EUV power output limitations utilizing dual or multiple source designs. Multiple source designs utilized in previous EUV prototypes did not appear to accommodate multiple light source matching and optimal Etendue. Achieving efficient Etendue might appear challenging.  However, utilizing Bragg cell mirrors it's possible that two (or more) EUV light sources might be simultaneously focused and phased within a single stepper IF. That considered, the total system MTBF (Mean Time Between Failure) might still be problematic as both sources will generate contaminating tin particulates which coat mirrors and critical wafer target surface areas. This phenomenon resulting in source/system/mirror contamination might be the limiting factor in Sn (tin) based LPP (Laser Produced Plasma) source technology.

To date, no one I've spoken with has an acceptable answer for how EUV power might be scaled to required HVM levels given current ASML LPP source designs. I'm sure we'd all be pleased to see ASML wheel a secret, high power EUV/HVM prototype onto the test lab floor, but over the past ten years many in the industry have become quite skeptical.

The larger question remains, why has the EUV program stalled and when will a technology break through occur? Over the years we have seen many semiconductor manufacturers and equipment vendors independently own and operate R&D programs. While there is great economy of scale in the collective funding of R&D by the large consortiums and foundry alliances, the investment in a singular technology as determined by committee vote can displace the valuable pursuit of multiple design concepts, effectively reducing opportunities for new scientific discovery and timely delivery of process solutions.

Given the newly announced R&D initiative by IBM, I will site an example worth revisiting.  During the late 1970's, semiconductor manufacturers recognized that greater control was required in diffusion tube processing utilizing dopant gases. It was realized that more precise control of dosimetry was required and a next generation process solution was considered. IBM released a request for quotation (RFQ) to equipment vendors for a high current ion implanter capable of ionizing dopant gases (typically boron, phosphorus and arsenic) and implanting the high energy ions directly in wafer substrates.  As there were no manufacturers of high current ion implanters at the time, no one bid on the IBM request. Given a no bid response, IBM engineers designed and built their own high current ion implantation system they called the Tachonic series (named after the surrounding Tachonic mountain range formations). Using off the shelf commercial parts where possible, a highly skilled IBM engineering group assembled (at great expense) a high current ion implantation system featuring mechanical beam scanning and precise dosimetry control. Several of the systems were built and were later retired when commercially manufactured systems became available. During the Tachonic series service lifetime, IBM experimented and mastered the mitigation of CMOS wafer surface charging with electron flood guns. Interestingly, AT&T Technologies and General Electric also produced their own similar (but different) high current ion implanters utilizing mechanical beam scanning techniques. There were no consortiums funding any singular concept for high current ion implantation hardware, and innovative designs soon gave birth to a high current implant industry. IBM's July 10, 2014 press release celebrates the many contributions it has made to the semiconductor manufacturing industry inclusive of process control, wafer fabrication technique and specialty tooling required for HVM. Could it be that the consortium of Intel, TSMC and Samsung funding EUV development at ASML has unintentionally displaced competitive R&D?  By accident or design, this is what has happened.

How might we shift gears and accelerate EUV development? The current EUV LPP program got its historic start when the Extreme Ultraviolet LLC (Intel, Motorola, Advanced Micro Devices and Micron Technology) contracted the DOE/Lawrence Livermore Labs to develop an LPP EUV source for the semiconductor industry. The decision was made that EUV was to be a laser based technology and consequently the EUV program evolved into the LPP platform currently marketed by ASML.

Early in my career I had the opportunity to visit Princeton Plasma Physics Laboratory and examine one of the first Tokamak fusion reactors there. The concern at the time was the inside surface wall of the reactor might be damaged by an unstable high temperature plasma. In later experiments at Princeton and fusion laboratories around the world, it was confirmed that turbulent plasma could be controlled using sheared flow techniques, reducing the potentially destructive effects of plasma contacting the chamber wall.

An innovative EUV source design introduced by a US based company called Zplasma utilizes z-pinch technology employing a patented sheared flow stabilization technique to produce both stable plasma pulse formation and 13.5nm EUV light emission.  Given the current LPP/EUV source design supplied by ASML/Cymer has yet to achieve HVM power levels, the EUV LLC consortium might want to pursue a similar EUV source development contract with Zplasma or a national laboratory experienced with z-pinch plasma technologies designed to optimize EUV output.  We must infuse new competitive thinking with competitive actions if we are to achieve a break through in EUV source power.  Hopefully IBM will contribute additional expertise to the EUV program given its increased R&D funding.  New inspiration and initiatives are needed to rekindle the diverse sources of innovation the semiconductor industry is known for.  

In the scheme of things we must consider how far we've advanced today's semiconductor technology.  Physicists at CERN in Switzerland operate a particle accelerator called the Large Hadron Collider. There on March 14, 2013 the existence of the theorized Higgs Boson was tentatively confirmed to have a mass of 125 GeV. The Higgs Boson is thought to impart the qualities of mass in matter and is sometimes referred to as “the God particle”. The search for the Higgs spanned 40 years and concluded after the construction of the Large Hadron Collider, costing an estimated $4.4 Billion (with a $9 Billion operational budget). By 2015 it is anticipated the acceleration energy at the LHC will reach 7 TeV, enabling particle collisions at 14 TeV. It seems ironic that on one hand physicists at CERN are utilizing high energy physics to smash and examine the components of sub-atomic structures, while semiconductor engineers implant ions at energies up to 2 MeV, purposefully creating sub-atomic lattice structures in flash memory cells. While we might debate “the God particle” reference ascribed to the Higgs Boson, the sound of Seri speaking from an iPhone must invoke a religious experience for her futurist creators.  It seems we're in a new line of business.

Please join me in supporting the National Photonics Initiative, SPIE and the International Year of Light 2015.

Thomas D. Jay 
Semiconductor Industry Consultant

Corporate, private entities or publications referenced or linked in this article are the respective owners of their logos, trademarks, service marks, media content and intellectual property.  Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated.

Acknowledgements and Reference Links


Lawrence Berkeley CXRO



IBM Press Release

National Ignition Facility

Princeton Plasma Physics Laboratory


CERN (Wikipedia)

Large Hadron Collider (Wikipedia)

National Photonics Initiative


The International Year of Light 2015

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