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Wednesday, August 7, 2013

The Continuing Evolution of Extreme Ultra Violet Lithography


On July 17, 2013 in a qualified safe harbor statement, an ASML press release (NASDAQ:ASML) announced its second quarter earnings and also indicated that its EUV platform, scanner imaging and overlay performance improved to levels enabling engagement with customers on a strategy targeting insertion at the 10nm logic node.  Additional discussions concerned strategies in which the first NXE:3300B systems running at currently available EUV power levels are utilized for production of future nodes at reduced throughput in place of mask strategies utilizing 193i multi-patterning techniques. Customers will be able to upgrade their systems as higher power levels become available and avoid a costly process transition from 193i to EUV HVM.  Combined with currently available multiple-patterning capabilities on existing 193i platforms, ASML could provide the best possible options for customers.  In the second quarter, ASML achieved good performance, stability and reliability of the pre-pulse source concept at power levels up to 55 Watts, and remains confident of targeted throughput of 70 wafers per hour in 2014.  ASML projects availability of upgraded systems with 125 wafer per hour throughput in 2015 provided further development of EUV power output progresses as planned. Additional strategies are being considered for continued funding of additional R&D on EUV.   450mm HVM insertion is anticipated in 2018.  News Source: Seeking Alpha.com 7/17/2013.

The semiconductor equipment industry participants driving the evolution of EUV (Extreme Ultra Violet) and nanometer scale lithography might be characterized as "tag team" players as process enabling technologies provided by an interactive vendor base will often trigger a cascade of new concepts and innovation frequently spawning “disruptive technologies”  The semiconductor lithography market is technologically unique, supporting many diverse products demanding application specific process solutions.  Although this market place can seem extraordinarily complex it is commonly bound by the semiconductor industry phenomenon known as Moore's Law which states that the number of transistors on semiconductor devices doubles approximately every two years, reducing costs.  During the past several years semiconductor lithographers have been pursuing the means to create a sufficiently powerful source of EUV (Extreme Ultra Violet) light for use in next generation lithography stepper/scanners.  These complex machines are used to mass produce semiconductor “computer chips” utilizing a photolithography process similar to conventional film photography, the difference being the “photo negative” is actually comprised of many individual photo masks (as many as 50 or more), providing the discrete image negatives required for each process layer in a complex semiconductor device.  EUV light source technology is being pursued as the emitted 13.5nm light's wavelength is short enough to produce high resolution circuit imaging for present and future 14, 10 and 7 nanometer scale device structures. Although several well established companies in the field of semiconductor lithography have participated in the development of EUV technology the expense and diminishing returns on investment have narrowed the playing field to a few.  Lithography giant ASML based in the Netherlands recently purchased a key lithography light source supplier, Cymer, in an effort to consolidate EUV development efforts and secure the timely delivery of critical source components.  Underscoring the strategic value of EUV lithography are recent investments made in ASML by Intel, Samsung, and TSMC which total more than $6 Billion. To date, ASML and Cymer have produced excellent EUV lithography imaging with an available light source power output approximating 55 watts.  This is about half the power required to support the throughput of high volume manufacturing (HVM).  After years of industry anticipation, delayed development of EUV power output has put some semiconductor industry professionals in an uneasy holding pattern.  Although multiple patterning techniques for 193i lithography provide feasible lithography solutions in the interim, most would prefer a simplified EUV lithography process solution requiring fewer mask levels at reduced cost.  In light of ASML's recent announcements some are reconsidering the current status of EUV lithography development and the implementation of available alternatives such as double patterning and Directed Self Assembly (DSA) techniques.  In an effort to gain additional insight and inspiration from established experts in the EUV community my inquiries revealed that many are reluctant to speak to the current situation and perhaps for good reason. It is difficult to speculatively comment on the efforts of lithography industry experts who have diligently achieved the excellent results obtained thus far.  It appears we've hit a physical wall which has temporarily stalled EUV development and delayed the HVM insertion time line.  As we have learned over the years, difficult tasks sometimes take longer to complete.

In the interim 24 months ahead we must also realize that the semiconductor industry will assimilate a new crop of scientists, electrical engineers, sales, marketing and application specialists along with the traditional complement of Wall Street industry analysts and investors.  To the new and uninitiated intelligentsia, EUV technology might require some explanation.  Educating new entrants to our industry is always a challenge.  As a technologist you might have a friend or relative who've asked about your work in semiconductors and observed their eyes glaze over as you explain.  As we pause to await news of higher EUV output power, I will utilize the available “dwell time” to provide an EUV primer for new industry participants and observers and hopefully fill in the blanks for our current, friends and colleagues.  Where to begin?                    


Plasma 101

Unlike solid, liquid or gas, plasma, the fourth state of matter exists within a narrow, low pressure domain approximating 1/760th of our atmosphere at sea level.  Positively ionized plasma can be created in this low pressure regime by inducing high energy electron collisions with gas molecules displacing orbital electrons normally found in the stable atoms comprising the gas.  The imparted electrical imbalance causes the gas molecules to gain a net positive charge as there are more positive protons remaining in the atoms/molecules than negatively charged electrons.  The resulting plasma is a glowing cloud of charged particles and gas molecules having a positive electrical potential and the conductivity of copper while simultaneously emitting light comprised of photons with the characteristic color of its elemental spectra.  Utilizing Italian physicist Torricelli’s scale, the pressure of the air at sea level is 760 Torr.  More specifically, the pressure at which electrical gas plasma can be created and sustained approximates 5x10-4 Torr, a near vacuum at less than 1/760th of the pressure of our atmosphere.  At an altitude of 84 kilometers above the earth and well below the international space station, the pressure in near outer space falls within this range and is conducive to the natural creation of plasma known as the aurora borealis.  This phenomenon occurs when high energy “solar wind” from the sun ionizes oxygen, nitrogen and other gases in the upper atmosphere in the presence of earth's magnetic field.  Back on terra firma, high vacuum technologists design and maintain carefully engineered process chambers simulating pressures ranging from ambient atmosphere to the ultra high vacuum of deep outer space.  Scientists and electrical engineers utilize these physical phenomena and resources to generate, contain and control high energy plasma by electrically ionizing specially selected process gases at precise pressures in high vacuum systems. Plasma etchers utilized in semiconductor wafer fabs were among the first process tools to adapt this technology.  In this application, plasma is generated to produce ions for etching semiconductor wafers.  The incidental light emitted from the plasma can be utilized to monitor the process.  The primary methods for ionizing these gases include hot cathode/filament electron discharge, microwave excitation, and RF (Radio Frequency) energy excitation.  Interestingly the Federal Communications Commission has designated special radio frequencies for use in plasma etch systems.   A common frequency utilized for RF plasma etchers is 13.56 MHz.  As a ham radio operator I am more spectrum conscious than most and when near a wafer fab I sometimes tune in with my mobile transceiver to listen for “etchers on the air”.  The received signal is not particularly exciting and is usually a continuous uninterrupted carrier wave sometimes producing a loud heterodyne when tuned in the single side band mode.

In this semiconductor manufacturing application of physics, positively charged high energy ions are created in these special plasma systems and utilized to etch semiconductor circuits on silicon wafers.  The ions having mass and kinetic energy bombard the surface of product wafers and selectively etch surfaces to form intricate device structures and circuit patterns from the metal film and materials left behind.  A variety of gases are utilized to etch process specific materials on product wafers.  Some of the gases utilized are also chemically reactive and can selectively enhance the etch rate of specific materials on a wafer's surface.  Other noble gases are chemically inert (non-reactive) and advantageous for a wide range of etch applications.  Plasma etch chambers emit a characteristic light whose primary color/wavelength is determined by the elemental composition of the process gas.  Argon gas for example emits a purple glow which is pleasing to the eye. This spectral phenomenon is often utilized as a process indicator to determine when a critical etch step must stop. While etching a thin film metal, a faint light emitting plasma with the metal's signature color/wavelength is also produced. Using optical end point detectors, process engineers can sample the spectrum of light emitted from the plasma to detect the metal's specific signature wavelength.  When this spectral signature disappears the metal etch process is deemed complete as there is no remaining metal being ionized.  This “end point” signal is typically used to automatically stop the etch cycle providing highly accurate process control and negates any manual intervention by wafer fab engineers.  A key observation of these phenomena are that elementally specific positively charged particle ions (mass specific) and photons (wavelength specific light) are created during the ionization process.  The science of plasma physics for etching semiconductor circuits has been refined over the years by companies like Applied Materials, Lam Research and Veeco Instruments (there are many others) however, the plasma physics required to produce 13.5nm EUV for lithography are quite different and much more challenging.  

Producing Extreme Ultra Violet Light With Plasma

For several years the semiconductor industry has been engaged in the research and development of next generation nanometer scale lithography requiring a precision stepper/scanner equipped with a 13.5nm light source.  For lithography applications, plasma is created for the purpose of generating light at specific wavelengths.  The production of ions and other charged particles is incidental and sometimes suppressed to avoid etching and erosion of sensitive components in the source and wafer stage. Utilizing the most current methods for producing this light, lithography research engineers create a plasma which emits 13.5nm EUV from the resulting ionization of xenon gas (Xe), or the solid metal tin (Sn).  As a gas, xenon ionizes easily but has a lower energy Conversion Efficiency (CE) than tin.  ASML has chosen solid tin as the plasma feed material for its EUV light source because of its higher energy conversion efficiency.  Creating an ionized tin plasma is more difficult and also creates unwanted particulates which can potentially contaminate EUV masks and product wafers. Although the 13.5nm spectra has been dubbed EUV (Extreme Ultra Violet) it can also be described as “soft x-ray” radiation or “vacuum EUV” as it is absorbed by many gases and propagates most efficiently in a high vacuum environment.  Extremely short wavelength EUV light will enable semiconductor lithographers to print ever smaller transistors and associated circuitry on computer chips reducing CD features (Critical Dimensions) down to nanometer scales and below.  Utilizing a current 22nm fabrication process, a state of the art Intel Quad core i7 microprocessor introduced in the year 2012 contains 1.4 billion transistors.  Moore's law marches on and future process nodes will soon shrink to 14, 10 and 7nm.  Imagine your smart phone's chip sets with the processing power of another billion or so transistors.


A Best Of Breed EUV Source?

As there has been significant wide ranging research on the subject of EUV source technology, I will focus on the most current technology utilized by ASML and will discuss possible alternately efficient means of EUV production. Having conducted research on past experimentation and published papers, I will direct attention to recent prior work having potential to enhance EUV source performance.  By “borrowing” concepts from the most promising efforts I will propose a possible “best of breed” hybrid EUV source design.  I suspect similar dialogue and debate has been conducted previously.  My intention is to foment new discussion which might yield solutions providing the EUV power output and performance required for HVM lithography (High Volume Manufacturing).   


ASML's EUV Source Design

ASML/Cymer's current technique for production of EUV light utilizes Laser Produced Plasma (LPP).  In this different approach to producing plasma, small droplets of tin approximating 30 microns in diameter are injected into an ionization source and targeted by a solid state “pre-pulse” laser.  The imparted energy from the pre-pulse laser enlarges the tin droplet and raises its energy state, providing a larger cross sectional profile for a more powerful 20 kilowatt CO2 laser.  After pre-pulse conditioning, the tin droplet is targeted with the larger CO2 laser resulting in the high energy evaporation and ionization of the tin, releasing 13.5nm EUV light as a result.  A continuous stream of tin droplets and sustained laser interaction produces stable EUV light output commensurate with requirements for precision lithography and dosimetry.  Utilizing this technique, current EUV power output levels of 55 watts have been achieved, about half the power required for HVM (High Volume Manufacturing).  In the quest for more EUV power output, I suspect ASML and Cymer will experiment with larger, more powerful lasers while optimizing other coincidental parameters.  While successfully producing EUV light, an Sn/LPP source produces a large number of tin particulates as the targeted tin droplet residue collects on exposed surface areas in the ion source and wafer stage. Reflective EUV optical mirror surfaces can lose efficiency (reflectivity) when coated with tin, while EUV masks and product wafers can be compromised if contaminated with particles as small as one nanometer.  A more recent technique for keeping surfaces clean is to direct a beam of hydrogen ions from a small, integral ion source at critical optics and wafer stage components.  Experiments implementing a hydrogen plasma clean cycle as part of a periodic maintenance regimen have also been suggested. The challenges in the design and implementation of EUV technology for high volume manufacturing are formidable.  


Z-Pinch Discharge Produced Plasma Source Technology

A Z-pinch source, consists of an insulated containment cylinder with electrodes attached on either end, mounted inside a vacuum chamber.  For the creation of EUV light emitting plasma, a gas such as SnH4 (Stannane) or xenon (Xe) is fed into the cylinder and pre-ionized with the resulting plasma having the electrical conductivity approximating that of copper.  A large pulse of electrical energy stored in a bank of capacitors or from a power supply is applied to the electrodes at the ends of the cylinder.  As a result, a large current flows through the electrically conductive plasma causing it to contract as a phenomenon known as the Lorentz force compels the mutual attraction of the ions flowing uniformly along the z-axis of the plasma. The term z-pinch is derived from the fact that the current flows along the z-axis of the plasma as it is being compressed and pinched. The contraction continues until the plasma becomes highly dense and further compression is resisted by the gas pressure comprising the plasma. Ultimately, the maximized “pinch” density releases a large burst of energy comprised of ions and characteristic spectral light.  In the case of SnH4 and Xe, Discharge Produced Plasma EUV light with a wavelength of 13.5 nanometers is emitted in the process.  A continuous, controlled flow of source gas and carefully timed high current pulses through the source cylinder repeat this cycle, sustaining the plasma and output of EUV light.  This is achieved by pulsing the power supply and the resulting high current flow through the conductive plasma between 6 and 8 thousand times a second.   A power supply pulsed at approximately 7 Khz usually delivers maximum output for this design.  Z-pinch operation can be further optimized by controlling the power supply frequency, pulse width and amplitude providing effective wave form control and regulation of power fed to the source.   With the power supply operating at a the relatively low frequency of 7 Khz, a computer operating at 1.5 to 2.0 GHz can be utilized to sample the sinusoidal/waveform input power and resulting EUV output at the wafer stage making it possible to close loop control associated lithography dosimetry and related functions.


Ushio's Sn/DPP EUV Source Design

At the SPIE 2007 International EUVL Symposium, Ushio published a paper on results obtained from experimentation conducted on a Discharge Produced Plasma EUV source utilizing SnH4 (Stannane) as the feed material: Development of Sn-fueled high-power DPP EUV Source Enabling HVM.  In this design a Z-pinch DPP source was fed with gaseous SnH4 providing the energy conversion efficiency of tin while affording the simplicity of source gas handling with conventional mass flow controllers and pressure measurement instruments.  Interestingly, Ushio's Discharge Produced Plasma (DPP) source produced 62 watts of EUV output utilizing gaseous SnH4 as compared with ASML's recently quoted EUV power output of 55 watts obtained with a Laser Produced Plasma sustained with source fed solid tin droplets.  A power output comparison of the two technologies builds a case for continued development of an SnH4 Discharge Produced Plasma EUV source with a more simplistic design.  An additional benefit of using SnH4 as a source feed material is it minimizes the erosion of electrodes and critical surfaces in the z-pinch tube.  

Zplasma's Xe/Stable DPP Z-Pinch Source With
Sheared Flow Stabilization (SFS)®

In my previous blog articles I've had the opportunity to interview Henry Berg, CEO of Zplasma, and discuss his company's Xenon based Discharge Produced Plasma EUV source.  Zplasma's Stable DPP source is quite different from the generic DPP description above.  Zplasma's stable pinch operation results from a patented, proprietary technique called Sheared Flow Stabilization (SFS)® which stabilizes the plasma and eliminates explosive pinch terminations. The stable pinch operation of an SFS design DPP source is required to produce the high power levels required for HVM lithography. As described by Henry Berg, there are six critical advantages to Zplasma's SFS source technology:

a) Longer Light Pulse: SFS pulses are 10 to 100 times longer due to their stable nature, allowing for more light collection.

b) High Power without High CE: Long SFS pulses and side-on optical collection access increase throughput and lower required CE, enabling HVM operation with xenon and eliminating the need for molten tin.

c) No Debris: SFS ends the plasma pinch without explosive termination, eliminating high-energy debris.

d) Low Instantaneous Power: SFS pulses allow for EUV light production without the high instantaneous power levels that cause electrode thermal stress and ablation.

e) Dose Uniformity: SFS allows the length of each EUV pulse to be adjusted under control of the power supply, allowing for extremely accurate dose uniformity.

f) Adjustable Geometry: SFS makes pinch geometry adjustable for optical matching to the stepper IF.
  
Given Discharge Produced Plasma (DPP) and Laser Produced Plasma (LPP) design concepts, how might we improve EUV power output and system performance?


Minimizing Source Plasma Opacity
Maximizing EUV light Output

EUV light emitted from a tin or xenon plasma discharge is partially absorbed by the opacity of source plasma.  More specifically, the 13.5nm light is readily absorbed by many gases and solid materials, inclusive of the low pressure vapor state of the tin or xenon utilized to create the plasma. This means that the intensity of the emitted EUV light diminishes as it is partially absorbed and diffused during its transit through the plasma cloud and transport to the stepper's intermediate focus (where the EUV light is collected).  A reduction in the rate of absorption and diffusion by the plasma can sometimes be achieved by reducing the pressure of the gas comprising the plasma. This has the effect of reducing the density of the plasma, lessening its opacity, and potentially increasing power output by increasing the transmission efficiency of the emitted EUV light.  This pressure adjustment is critical as the plasma will be extinguished if the pressure is too low (insufficient gas density/pressure to sustain the plasma) and will similarly cease to ionize if the pressure is too high. Experimentation is required to determine the optimal pressure and plasma density for maximum production and transmission of EUV light.  I suspect ASML has optimized this parameter on their Sn/LPP EUV source.  This technique is discussed in a 2005 paper:  Comparison of experimental and simulated extreme ultraviolet spectra of xenon and tin discharges by E.R. Keift, K. Garloff, J.J.A.M. van der Mullen and V. Banine.  


Maximizing the Transmission Efficiency
 of EUV Light to the Wafer Stage

To carry the EUV transmission efficiency discussion further, in some EUV system designs the wafer stage chamber is maintained at the same vacuum pressure (approximately 5x10-4 Torr), as the plasma source chamber and share the vacuum environment sustained by the pressure controllers and vacuum pumps supporting the EUV plasma. The pressure inside the wafer stage area is also critical as additional absorption and diffusion of the EUV light can occur there during transit from the intermediate focus coupling (IF) to the wafer stage.  Reductions of EUV energy propagation efficiency in the wafer stage chamber can be pressure related and contribute to path loss concerns exemplified in the source plasma opacity discussion above.  It is probable that higher levels of EUV dosing can be obtained by maintaining the wafer stage chamber under high vacuum pressure at <1x10-7 Torr. 

An excellent example of increased energy transfer efficiency under high vacuum conditions and the resulting effects on lithography are illustrated in a 2006 Nano Letters paper by Benjamin D. Myers and Vinayak P. Dravid, Variable Pressure Electron Beam Lithography (VP-eBL): A New Tool For Direct Patterning of Nanometer Scale Features on Substrates With Low Electrical Conductivity.  I found this paper quite interesting in that it addresses concerns common to both EUV and eBeam technologies.  The primary purpose of this paper was to illustrate a methodology for mitigating surface charging effects on electrically insulated wafer substrates patterned with eBeam lithography while simultaneously optimizing the resolution of the patterned images.  The paper also illustrates how differences in vacuum pressure effect eBeam (energy) propagation.  In the experiment, a differentially pumped vacuum system maintained an electron beam column under high vacuum while enabling operation of the wafer stage within pressures ranging from high vacuum to 3 Torr.  It was determined that a decrease in beam-gas path length (BGPL) and resulting electron beam scattering occurring at higher pressures mitigated surface charging and secondary electron proximity effects while enhancing image resolution.  However, the beam scattering also reduced the number of electrons available to dose the patterned resist requiring longer write times.  Longer write times or specialized dose requirements can now be optimized with computational lithography techniques inclusive of shot tasking and dose modulation.  To follow the discussion of exhibits in this paper, click on the link above. In Figure 1, exhibit (A) illustrates the insulated substrate surface charge induced displacement and distortion of eBeam imaging at high vacuum pressure.  Subsequent improvement in image resolution and accuracy are illustrated in exhibit (B) at .4 Torr, and in exhibit (C) at 1 Torr.  In Figure 2, Exhibits (A) through (D) and similarly Figure 3, Exhibits (A) through (C), illustrate eBeam induced surface trenching in the resist which decreases when the pressure is increased.  These examples illustrate the increase in energy transfer efficiency under high vacuum conditions and resulting decrease at higher pressures.  Figure 4, illustrates how electron beam dose requirements increase at higher gas pressures along with the interactive effect on minimum line width.  While there have been studies and process gas specific absorption coefficients established for electron beams and spectral light across a range of pressure regimes, it is well recognized that both forms of energy propagate most efficiently in a high vacuum environment, hence the term “vacuum EUV”. 

It follows that an EUV source and wafer stage chamber maintained at separate optimal pressure levels, approximately 5x10-4 Torr for the source (plasma opacity optimized),  and <10-7 Torr for the wafer stage chamber, more efficient transfer of EUV light can likely be obtained. This scenario requires a means of isolating the two vacuum chambers, perhaps by differential pumping, and transferring the EUV light through a transparent window or aperture at the intermediate focus (IF).  There are candidates for low loss EUV window material which could facilitate such a design.  In addition, there is a patented EUV source design featuring a differentially pumped source and wafer stage chamber coupled by a gas flow/conduction limiting optical aperture which efficiently conducts the EUV light across the two pressure regimes. http://www.google.com/patents/US6576912


Dueling Etendue – A Hybrid Dual DPP Source Design
 to Double Power Output

The search for high power EUV production techniques has been primarily focused on identification of energy conversion efficient source materials (solid and gaseous) and the most efficient means of ionizing them.  Recent research has determined that the best two ionization techniques are Discharge Produced Plasma (DPP) and Laser Produced Plasma (LPP).  As I point out in this article, the two techniques seem to be tied at maximum EUV power levels of 62 watts for DPP and 55 watts for LPP.  An approach to achieving higher power levels might be to operate two DPP sources simultaneously within one vacuum system, theoretically generating twice the power output.  The challenge would be optically coupling two sources to the stepper IF to truly double the power.  This might not be easily achieved.   Simultaneously capturing the maximum brilliance of two plasma sources could be challenging as the hardware interface to the IF must accommodate the optimal plasma profile angles for two discrete light sources to effect the most efficient etendue.  It's possible Bragg Cell EUV mirrors could be utilized to assist in effecting dual source DPP etendue.  Any concerns with absorptive losses from the Bragg Cell mirrors would be negated by the additional power afforded by the dual source design.

In my opinion a good candidate design technology for a hybrid EUV source resides with Zplasma.  The original system built by Zplasma utilized Xe as its source gas feed which produced a 2% bandwidth energy conversion efficiency (CE) of 0.5% which is low, however the efficiency will increase to 1.5% with a power supply optimized for the source.  By substituting Xe with SnH4, the energy conversion efficiency could be increased further to become competitive with Sn Laser Produced Plasma efforts to date. In addition to the increase in CE, higher EUV output power levels might be obtained if Zplasma's patented Sheared Flow Stabilization Z-pinch performs as well with SnH4 as it does with Xe.  Zplasma's system design might also accommodate the concept of Dual DPP sources as etendue match concerns might be minimized by its z-pinch source characteristics affording side on collection of light from the plasma.  In addition, the DPP configuration could accommodate an optional H2 plasma clean maintenance regimen.  A successful technique utilized by Gigaphoton in its source development program minimizes tin (Sn) particulate contamination by optimal positioning of a superconducting magnet in the source which deflects tin particles away from critical wafer stage and optical components.  Assuming a viable hybrid EUV source design is identified, how might further R&D funding be obtained given the current economic climate?


A Proposal for a New National Photonics Initiative Agenda Funding High Priority Challenges
 to Manufacturing

An important SPIE co-sponsored initiative took place on February 28, 2013 in Washington, DC, titled, “Optics and Photonics: Lighting a Path to the Future.”  Other organizations co-sponsoring the event included the IEEE Photonics Society, Optical Society of America (OSA), IEEE Photonics Society,  American Physical Society, and the Laser Institute of America.  The event was attended by many government agencies who traditionally sponsor research. The goal of the conference was to foster better government collaboration with American optics and photonics industries and forge a National Photonics Initiative (NPI).  The value of this proposed initiative is best exemplified by recent (non-government) semiconductor industry manufacturers' investments in ASML and Cymer.  The collaboration of industry and government in key photonic and optical science endeavors could distribute R&D expenditures among participants and reduce costs across many disciplines. While I was researching and writing this blog article, the benefits of a coordinated NPI program became more apparent.  After reviewing the many technical papers written on the subject of EUV and related technologies, I believe it is accurate to say that the level of participation by private industry, universities and government sponsored funding is probably unprecedented, and has created a reciprocally proportionate wealth of intellectual property and patent filings spanning many entities and corporations.  While we all support the concept of independent research, competitive concerns with ownership of applicable intellectual property may have slowed investment in the development of the EUV program. It is my opinion that a hybrid EUV source with superior power output and HVM performance might be assembled from the assortment of promising technologies and IP developed thus far.  Should a hybrid EUV concept be successfully proven, ensuing IP cross licensing concerns could potentially inhibit cooperation and progress.  This concern has been addressed previously by SEMATECH and other groups cooperatively sponsoring other past and present research programs.  The current pause in the pace of EUV development should foment renewed enthusiasm for jointly developed technology, intellectual property and reduction of R&D costs outside the domain of the foundries in order to prevent further stratification and/or dissolution of the traditional semiconductor equipment vendor base.  

On July 25, 2013 I received the following communication from NIST from which I have excerpted the following:

MEMORANDUM FOR Advanced Manufacturing Distribution 
From: The NIST Advanced Manufacturing Technology Consortia (AMTech) Program Team

“It is my pleasure to inform you that the National Institute of Standards and Technology (NIST) has released a Federal Funding Opportunity (FFO) for the Advanced Manufacturing Technology Consortia (AMTech) Program.  This is a new competition for awards to establish new or strengthen existing industry-led consortia in planning research that addresses high-priority challenges impeding the growth of advanced manufacturing in the United States.  NIST anticipates awarding $4 million in early 2014 as a result of this AMTech announcement.  Awards are expected to be up to two-years in duration and range between about $250,000 and $500,000.  As a leading voice in advanced manufacturing, we believe your members or constituents may have interest in AMTech and this newly announced funding opportunity.  AMTech-supported consortia will identify and prioritize long-term, pre-competitive industrial research needs; enable technology development; and create the infrastructure necessary for more efficient transfer of technology.  Teaming and partnerships are strongly encouraged including participation by the full value chain, including small-and mid-sized firms.  By convening key players across the entire innovation life cycle, the objectives of the AMTech Program are to eliminate critical barriers to innovation; increase the efficiency of domestic innovation efforts; and collapse the time scale to deliver new products and services based on scientific and technological advances. The end goal will be a growth of advanced manufacturing in the U.S. and an increase in the global competitiveness of U.S. Companies.  The AMTech Program will host two webinars on August 15, 2013, and August 20, 2013, at 2:00 p.m. Eastern time.  Participants are required to register in advance.  The events will offer guidance on the AMTech Program and preparing proposals, and will provide an opportunity to answer questions from the public about the program.  Participation in the free event is not required to submit an application.  Information on and registration for the event is available at www.nist.gov/ampo.  To assist in identifying potential collaborators for a consortium, the AMTech Program is creating a LinkedIn group where individuals can provide their area(s) of interest and communicate with each other.  Visit www.nist.gov/ampo for more information about joining.”

In considering this proactive initiative by NIST, I believe it is accurate to state that timely availability of EUV lithography technology is one of the high-priority challenges impeding the growth of more advanced manufacturing in the United States.

I propose that SPIE and the industry groups comprising the National Photonics Initiative consider establishing an additional agenda coordinated with SEMATECH to pursue government funding of advanced research in EUV development.  Further, there should be emphasis on directing available grant funding to the many promising start up companies whose entrepreneurial potential for technological contribution have been precluded by the prevailing economic climate in Silicon Valley, Wall Street and the larger U.S. economy.  We all applaud the cooperation of major players such as Intel, Samsung, and TSMC as they collectively support the efforts of ASML, but we must also ensure proactive support for promising, small business based entrepreneurial start up companies that have traditionally made the best and brightest contributions to Silicon Valley and the semiconductor industry.

Thomas D. Jay
Semiconductor Industry Consultant
Thomas.Dale.Jay@gmail.com
ThomasDaleJay.blogspot.com
Thomas D. Jay  Investment Commentary
Thomas D. Jay  YouTube Channel








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Corporate or private entities mentioned in this article are the respective owners of their logos, trademarks, service marks and intellectual property. Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated.

Correction:  A previous reference in this article was made crediting Ushio for a technique utilizing a superconducting magnetic field to mitigate tin particulate debris.  This statement was made in error and corrected on August 8, 2013.  Gigaphoton developed the superconducting magnet particulate mitigation technique as reported by Business Wire on July 1, 2013.  My apologies to Gigaphoton and Ushio for this unintentional error.  
Thomas D. Jay, August 8, 2013

Acknowledgments and Links

ASML News Release Source: Seeking Alpha.com 7/17/2013

Intel's Quad Core i7 Microprocessor
Intel Corporation, You Tube

ASML/Cymer's current technique for production of EUV light, ASML, You Tube

The challenges in the design and implementation of EUV technology for high volume manufacturing are formidable,
Jos Benschop, ASML, You Tube

Z-Pinch DPP Source Reference, Wikipedia.org

Development of Sn-fueled high-power DPP EUV Source Enabling HVM, Yusuke Teramoto, Zenzo Narihiro, Daiki Yamatani, Takuma Yokoyama, Kazunori Bessho,
Yuki Joshima, Takahiro Shirai, Shinsuke Mouri, Takahiro Inoue, Hiroshi Mizokoshi, Gohta Niimi*, Tomonao Hosokai*, Hironobu Yabuta, Kohkan C. Paul, Tetsu Takemura, Toshio Yokota, Kiyoyuki Kabuki, Koji Miyauchi, Kazuaki Hotta, and Hiroto Sato Gotenba Branch, Hiratsuka Research and Development Center, Extreme Ultraviolet Lithography System Development Association  *Ushio Inc.

www.zplasma.com, Henry Berg, CEO, Zplasma, Inc.

Comparison of experimental and simulated extreme ultraviolet spectra of xenon and tin discharges by E.R. Keift, K. Garloff, J.J.A.M. van der Mullen and V. Banine

Variable Pressure Electron Beam Lithography (VP-eBL): A New Tool For Direct Patterning of Nanometer Scale Features on Substrates With Low Electrical Conductivity, Benjamin D. Myers and Vinayak P. Dravid

http://www.google.com/patents/US6576912

www.nist.gov/ampo

National Photonics Initiative

NPI Agenda

SEMATECH





Wednesday, May 15, 2013

The Strategic Positioning of Electron Beam Lithography - The Pellicle Brief


In my recent blog post of March 20, Report on Recent SPIE Activities – Spring 2013, I spoke to the issues gating the development of EUV (Extreme Ultra Violet) lithography and its projected HVM (High Volume Manufacturing) insertion time line established by the semiconductor industry.  I made brief mention of current and alternative state of the art technologies enabling nanometer scale lithography; 193i (193nm immersion lithography), EBL (Electron Beam Lithography),  NIL (Nano Imprint Lithography), and DSA (Directed Self Assembly) techniques. I received many comments requesting my opinion on the viability of EBL for HVM and the role it might play along side the larger scale implementation of EUV.  On April 10, 2013 I posted a follow on article “Direct Write E-beam Lithography; Complementary Technology in the Fab” which described the historic (1980s and later) use of EBL as a direct write lithography production tool supplementing existing optical lithography systems in the wafer fab.  EBL has evolved over the years and several companies are activity developing direct write systems intended to provide complementary HVM capabilities for current 193i and future EUV lithography.  There has been so much recent emphasis placed on EUV that it's possible many outside (and inside) the semiconductor industry are unaware of the momentum established by the eBeam Initiative.  The EBL story is much larger than most realize and requires additional amplification. It is imperative that technologists and investors in (and outside) the highly specialized semiconductor industry fully appreciate the recent advances in EBL and computational lithography that will continue to provide game changing advancements in the extension of Moore's Law.

Historically, EBL (Electron Beam Lithography) has been utilized in the laboratory for R&D and as the tool of choice to provide the best possible accuracy and precision in the fabrication of photo masks (the master “negative” image plates used to print circuit patterns on a semiconductor wafer).  Billions of complex geometric circuit patterns and device structures comprising a state of the art computer chip are designed, rendered and stored on powerful computer systems.  To fabricate a photomask, the stored geometric circuit data is downloaded to an electron beam lithography system which precisely “writes” the patterns on a blank photomask coated with a special ebeam resist (which is the film on which the master circuit image is printed).  After processing, the photomask becomes the photo negative utilized to repetitively print the circuit on silicon wafers moving through the production line (a process called step and repeat (the optical lithography machines are often referred to as “steppers”).  This traditional technique is currently utilized to produce mask sets for state of the art lithography steppers inclusive of 193i HVM and pilot line 13.5nm EUV lithography.  “Mask sets” can cost millions of dollars to produce as computational lithography corrections and computer rendering of the images are cost intensive and must produce perfectly written EBL masters.  Each computer chip can have as many as fifty or more mask levels comprising the many layers in its circuit design, with each mask level taking approximately a day to produce.  It is estimated that the cost of a mask set for the 20nm node will approximate $10 million considering the design and render time on powerful computers. 

In addition to writing photo masks, semiconductor design engineers recognize that EBL systems can write the same patterns directly to a silicon wafer with electron beams negating the necessity of the photo masks but incurring costly write time for each wafer.  Because DWEB (Direct Write Electron Beam) lithography has historically cost more than printing wafers with photomasks, its production use has been limited to very specialized high value semiconductor products (and photo masks).

Fast forward 2013.  Recent advances in computing power, data storage density and computational lithography techniques are closing the cost differential between DWEB manufacturing and 193i photomask/EUV HVM.  With mask fabrication costs soaring and EUV steppers priced at $125 million, the cost delta for selected applications could continue to close as EBL begins to compete with rule based mask design and wafer fabrication above the 32nm nodes, and the later implementation of Model Based Mask Data Prep (MB-MDP) for <20nm nodes.  To further reduce the costs associated with lengthy electron beam write times, many propose utilizing EBL cluster tools comprised of as many as ten DWEB modules to enhance throughput.  Cluster DWEB tools could be configured to match the throughput of production steppers.  However, the unambiguous identification of the cost/throughput intercept point (the point when DWEB cluster and 193/EUV production throughput costs become equal) must be conclusively achieved.  This will take some time as many key technologies enhancing EBL are continually evolving.  In the interim, EBL provides the precision and accuracy required to produce all of the key nanometer scale lithography enablers in the semiconductor industry.

As we negotiate the path to ever smaller CDs (Critical Dimensions) it's important to note:

  • EBL has been historically used to fabricate traditional optical lithography masks, 193i masks, EUV masks, NIL (Nano Imprint Lithography) molds, and enables maskless DWEB (Direct Write Electron Beam) fabrication of wafers. 
  • EBL has better DOF than EUV (and 193i).
  • With better DOF, resolution and electron beam spot size control, maskless EBL could be better suited for highly resolved 20nm and <14 nm lithography.
EBL has the potential to complement EUV HVM and could become the lithography tool of choice for future process nodes should EBL cluster tool throughput become competitive with EUV stepper throughput performance.  If EUV source power development stalls at its current power level of approximately 50 – 60 watts, this could become the intercept point for comparable stepper/EBL throughput near the 20 nm node (inclusive of acknowledged EBL write time). Cluster EBL systems can also be scaled to match enhanced EUV productivity provided data storage, throughput issues and eBeam Initiative Road Map plans are realized.

Interestingly, this month on May 9, Ushio announced it will sell its EUV service business to ASML and discontinue further R&D on EUV source technology. (News source: Chip and Dips, Japan)  Ushio's subsidiary Xtreme  Technologies was competing with Cymer for EUV source business with ASML.  In a vote of confidence and expediency ASML recently purchased Cymer to secure timely delivery of EUV source technology.  Thirty of the Ushio staff in Germany will be assimilated by ASML in order to support its on going operations there. 

The eBeam Initiative was organized in 2009 to facilitate a cooperative forum for discussion of critical issues confronting both EBL and the larger optical photomask design community.  Aki Fujimura is the CEO of D2S, Inc. and also serves as the managing company sponsor of the eBeam Initiative.  Comprised of over 43 member companies and advisers, the eBeam Initiative membership cooperatively collaborates on research efforts in the areas of advanced mask design, computational lithography and related semiconductor process knowledge.  One of the group's projects, Model Based Mask Data Prep (MB-MDP) holds great promise for resolving many mask quality issues.  The introduction of computational lithography techniques for error correction of optical distortions on masks (called Model Based Mask Fabrication) for 193i and EUV process nodes can incur significant additional analysis, write time and expense. Currently, accurate reproduction of < 32nm nanometer scale CDs for 193i and EUV often requires the implementation of OPC (Optical Proximity Correction).  Ideally, the mask pattern transferred to the wafer during photo exposure should perfectly replicate the mask image.  Often times patterns printed on the wafer are distorted due to stepper lens aberrations, phase distortions, diffraction related blurring and under exposure.  Computational analysis of the printed distortions, stepper optics and dose parameters can yield modified mask patterns which will print optically corrected images on a silicon wafer.  Although there are no optics associated with EBL, similar proximity effect distortions can appear on printed wafers after fabrication with electron beams.  Secondary electron emissions created near the impinging electron beam's intended write area can expose adjacent areas on the wafer creating unwanted pattern distortions.  Variations of a circuit pattern's geometry and density can result in LER, poor CDU and shot noise. For further reference: Naoya Hayashi of Dai Nippon Printing Co., Ltd recently discussed Computational Lithography Requirements & Challenges for Mask Making.

Shot Noise
Shot noise is a phenomenon common to both EUV and EBL (for similar reasons).  A low EUV photon count can contribute to optical stepper dose control issues resulting in LER (Line Edge Roughness), poor contact hole resolution, and reduction in throughput.  Current EUV power output levels are insufficient and contribute to this problem.  In contrast, EBL technology provides the ability to control beam current and energy over a broad range eliminating any analogous concerns with EUV source power output.  As an example, Multibeam's ebeam source energy level is adjustable from 5-50KeV.  In spite of this inherent advantage, it's possible that for any given chip, an electron beam with a specific process optimized energy might still under or over dose a device and surrounding structures which can have wide ranging variations in size and geometric complexities.  Research continues to minimize shot noise issues for both EUV and EBL technologies.

Design for eBeam Mask Methodology (DFeB)
The eBeam Initiative has embarked on a program called the DFeB Road map (Design For eBeam see road map page 7), an industry strategy aimed at the optimization of mask fabrication techniques for scaling <20nm lithography, encompassing OPC (Optical Proximity Correction) for optical lithography, and Proximity Effect mitigation for EBL.  Computational lithography techniques can be utilized to resolve complex mask error issues by implementing Model Based Mask Data Prep (MB-MDP).  Analysis of OPC and/or eBeam proximity effect error data can be utilized to create software corrected mask patterns comprised of overlapping eBeam shots, circles and other optimized geometric shapes.  Additional thermal analysis of overlapping shots and checks on dose accuracy can provide an enhanced data set enabling a double simulation of mask fabrication and performance for more accurate analysis and prediction of wafer quality.

The Design for eBeam Mask methodology (DFeB) can help resolve many issues inclusive of shot noise and uniformity concerns.  Ryan Pearman discusses elements of computational lithography and how as a component of the DFeB strategy it can enable the segmentation and independent management of critical device patterns, structures and exposure dose on a chip.  EBL mask quality can also be enhanced utilizing VSB (Variable Shaped Beam for specific tasks) to increase resolution and write accuracy, enabling the creation of specialized structures and overlapping patterns.  Model Based Mask Data Prep (MB-MDP) can be implemented so that discrete structures and patterns can be addressed individually in computer memory such that each can be assigned specific shot tasking with unique eBeam energies providing control of dose margin.  Called Shot or Dose Modulation, this is a new technique of assigning a unique electron beam energy and current to a specific pattern(s) or geometry stored in memory.  This can enhance eBeam dose control accuracy over a chip (and wafer) potentially improving LER and minimizing shot noise typically encountered with contact holes and complex geometries.  Conventional MPC can not address these problems. 

While Model Based Mask Data Prep (MB-MDP) holds great promise for resolving many mask quality issues, it could further complicate Tennant's Law which observes that EBL throughput drops dramatically as geometries get smaller and resolution improves.  The time required to write specific, model based process enhancing parameters for a single chip (such as proximity correction, overlapping patterns, shot count assignments and dose modulation) can probably be minimized by efficiently writing, compiling and compressing the program code as exemplified by recent efforts at Nuflare.  It seems we might require a Tennant's Law Compensator (TLC).  To recover CPU time lost to MB-MDP, more powerful computers and network throughput will be required.  Should optimized DFeB mask designs be compiled for maskless EBL production, other major concerns in implementing cluster tools are the enormous data transfer rates and storage capacity required to replicate a large library of pattern layers.  A reference document provided by Multibeam indicated that 2D lithography requirements for a single process layer currently approximates ten terabytes.  EBL write speeds can reach several gigabytes per second with large cluster system data flow speeds at terabytes per second.  Admittedly this represents a challenge.  Perhaps there are answers at hand.

“Recently I received email communication from John S. Petersen, principal of his company, Periodic Structures/Petersen Advanced Lithography and SPIE Fellow. John has been following my blog articles on lithography and we began an email discussion of EBL data throughput issues.  John categorized his work as “fringe research” indicating he was collaborating with another company to provide a 13Tb/Sec data path for eBeam lithography.  John commented, “Our data path goal achieves the desired ideal in that with it we could attain the same throughput of an HVM EUV tool but there is no eBeam tool yet capable of using the pipe.”  John's other “fringe research” of interest includes 2-color STED (STimulated Emission-Depletion) lithography for sub-11 nm imaging in HVM and computational microscopy.  In response my comment was, “Interestingly the fringe is becoming more common place as research such as yours finds its way into manufacturing.”  I've obtained permission from John Petersen to include mention of his work in this article.   John advises that both of his development efforts are gated by the focus on EUV that pushes them to the fringe.  Those  interested in John's work may contact him at his email address, jpetersen@advlitho.com.

NVIDIA recently introduced the Kepler K10 Accelerator card for PCs which is capable of Peak Single Precision floating point performance of 4.58 teraflops and Peak Double Precision floating point performance of 0.19 Teraflops with 8GB of GDDR5 memory.  Up to four of the accelerator cards can be installed in parallel to achieve 18.32 Teraflops single and 0.76 Teraflops Peak Double precision calculations utilizing 32GB of memory.  Clusters of these systems on a network near the fab could provide the CPU power required for MB-MDP mask enhancement support.  I have to admit I was geeked and curious about the K10's price and Googled to discover that the NVIDIA K10 Accelerator card is available at Amazon.com for $2,750 (I didn't buy one).  A small Windows 7 based desk top super computer is now a reality.   I suspect than when CPU resource is addressed strategically the larger fab data throughput concern is a non-issue for companies such as Intel and the large foundries. 

Production Throughput of Cluster EBL
EBL cluster systems could have inherent advantages in over all efficiency possibly offsetting Tennant's Law.  Assuming an EBL cluster is sized to match stepper throughput, it's possible that during partial maintenance (the cluster runs at 50% throughput while half of the modules are serviced) Tennant's Law could be off set as a stepper with the same throughput would cease production completely while being serviced.

Mask Error Enhancement Function (MEEF)
MEEF (Mask Error Enhancement Function) is a measure of optical mask quality illustrating the difference between a mask's master image and the corresponding fidelity of its printed image.  Images are not always replicated precisely when printed as optical effects can cause pattern feature bias issues.  Smaller features are prone to larger bias errors while large features exhibit smaller errors.  These errors can be magnified when changing the stepper image bias.  Plotting the linearity of these differences can be challenging when optimizing mask fabrication.  MEEF data and derived corrective techniques have traditionally been the domain of optical mask quality control.  Recent DFeB (Design for eBeam) initiatives reflect the fact that eBeam is maskless lithography requiring similar techniques used for analysis of printed wafer quality.  Anthony Adamov explains the introduction of eMEEF which similarly samples image data to provide corrective guidance.  eMEEF data can be derived and analyzed from two identical images written at different beam energies.  As optimized eBeam image quality is typically better than that achieved with an optical mask, eMEEF data looks better than its comparative optical (MEEF) counterpart. 

Particulate Reduction and Management
It would seem that EBL systems might be inherently cleaner than a Laser/Sn EUV stepper from a particulate control perspective.  Laser/Sn based EUV sources generate large numbers of tin particulates necessitating hardware shielding, or magnetic field mitigation techniques to protect optics and critical surface areas near the source and wafer stage.  As there is no mask transfer activity or pellicle handling associated with EBL, remaining concerns might include residual carbon particles accumulated on eBeam optics or more traditional “particle added” wafer handling issues. Particulate contamination of an EUV mask is a critical concern and can compromise weeks of work and millions of dollars invested in mask fabrication.   A recent SPIE News Room article features a paper, Repairing photomasks by nanomachining by Gregory McIntyre, Emily Gallaghar, Mark Lawliss, Tod Robinson, Michael Archuletta and Ron Bozak.  The paper illustrates a repair technique for use on highly sensitive EUV masks.  Particles can be added during mask handling and can also be intrinsic to mask blank materials. Tests conducted on a six inch EUV photomask revealed that a single 1nm tall particle created a multilayer defect which rendered the mask useless.  In an ingenious repair effort, the authors of the paper employed the use of an AFM (Atomic Force Microscope) to nanomachine and repair the site of the 1nm particle induced defect.  The operation was a success and illustrates the high costs associated with mask management for 13.5nm EUV.  As there is no mask or pellicle hardware associated with EBL, resulting longer term mask cost and salvage/repair savings could provide an additional cost offset in favor of cluster EBL for HVM.    

As a proactive member of the eBeam Initiative, David K. Lam, Ph.D., the founder of Lam Research, CEO and Chairman of Multibeam Corporation proposes an interesting interim market entry for EBL.  Dr. Lam discusses the utilization of EBL for what has been termed CEBL (Complementary E-Beam Lithography) which facilitates line cuts on 1D optimized chip designs, possibly displacing multiple patterning with established 193i lithography techniques.

David K. Lam, Ph.D.,  Founder of Lam Research, CEO and Chairman of Multibeam Comments on Multibeam's Market Entry Strategy and System Design Features:

Yan Borodovsky, Ph.D., Intel’s lithography guru, envisioned e-beam lithography working as a cost-efficient complement to optical lithography during a presentation he made in 2010.  Supporting the practicality of his vision was the shift that major IC manufacturers were making from using irregular two-directional (2D) patterning to regular “gridded” unidirectional (1D) patterning. Borodovsky’s vision has given rise to Complementary E-Beam Lithography (CEBL), a new class of semiconductor production equipment.”

There has been much past and present speculation of where Electron Beam Lithography might play a role in the wafer fab as either a complementary tool or a competitive challenge to 193i and future EUV HVM.  In preparing this article I thought it important to include discussion with a real, viable semiconductor equipment manufacturer positioned for HVM market entry with a well defined cluster EBL strategy.  Having founded Lam Research, David K. Lam, P.h.D. has again demonstrated his industry insight in positioning Multibeam for timely entry to the nanometer scale semiconductor lithography HVM environment.  Communicating with Dr. Lam via email I forwarded him a list of questions in an effort to interrogatively summarize Multibeam's approach to the current and future semiconductor market.  The questions are mine with responses provided by Dr. Lam in a recent email exchange:     
Thomas D. Jay, Semiconductor Industry Consultant
“What prompted the semiconductor industry's transition from 2D to 1D patterning?”

David K. Lam, P.h.D., Chairman and CEO, Multibeam
“By shifting from an irregular 2D to a “gridded” 1D design layout style, leading chip makers are now defining circuit functions with simpler unidirectional “lines” and “cuts” – which enables device scaling beyond what is possible using conventional 2D random layout and paves the way for complementary lithography solutions. Multibeam’s Complementary E-Beam Lithography (CEBL) offers a compelling complement to both existing 193i and EUV lithography as it can “cut” lines at critical layers and do so at relaxed tolerances without the need for costly masks.”

Thomas D. Jay
“What specific criteria was utilized to define Multibeam's anticipated target market for 1D CEBL patterning?”

David K. Lam, P.h.D.
“The use of “Gridded” 1D Layout Style by leading chip makers started in 2007.  Since then, IC designers have increasingly adopted this unidirectional “gridded” 1D layout style to overcome a major roadblock to scaling and manufacturing advanced logic devices. Patterning lines-and-cuts involves printing and cutting gratings. While 193i remains excellent for printing the lines, cutting the lines is a different matter.  As nodes advance, optical cutting requires complex optical proximity correction (OPC), multiple patterning, and expensive cut masks.  CEBL promises a compelling cost-efficient lithography option. Multibeam expects its CEBL to be used by both IDMs and Foundries to reduce optical lithography costs in processing both complex logic and memory chips at high volumes.  Moreover, when EUV becomes available and is used to pattern below 13.5nm, there will be severe OPC and other resolution problems, which CEBL can help resolve by performing line cutting and eliminating costly multi-patterning at critical layers.  Optical lithography line-cutting is very expensive due to the soaring cost of mask sets.  Accordingly, CEBL offers a compelling alternative to “cut” the lines with no masks at certain critical layers.  Thus CEBL can work hand-in-hand with optical lithography, which would continue to reliably print the lines to demanding critical dimensions and line edge roughness specifications.” 


Thomas D. Jay
“Given the high costs of data storage, the computational overhead associated with EBL and Model Based Mask Data Prep (MB-MDP), could the migration to CEBL 1D HVM challenge Tennant's Law and result in higher manufacturing costs?”

David K. Lam, P.h.D.
“The Shift to “Gridded” 1D Layout Style combined with Multibeam's multi-column approach streamlines the storage and transfer rate of data patterns; as much as three orders of magnitude less pattern data and lower transfer rate are required.  Multibeam leverages the 1D-layout trend in developing its multi-column CEBL system to pattern line-cuts and complement optical line-printing. 1D + Optical + CEBL enable advanced logic devices to be fabricated cost-efficiently in HVM environments.”


Thomas D. Jay
“Multibeam has opted to enter the wafer fab market with 300mm wafer tooling. Are there plans to expand to 450mm?”

David K. Lam, P.h.D.
“Multibeam’s multi column architecture can be easily scaled to pattern 450mm wafers with no throughput penalty.  Moreover, multiple modules can be integrated into a “cluster tool” to boost throughput as each module writes on a separate wafer, reaching a combined throughput level compatible with high-volume manufacturing (HVM) production flow. The multi-level redundancy of Multibeam’s proprietary multi-column architecture combined with today’s high-reliability thermal field emitter source assure an uptime, MTBF, and equipment utilization comparable to process equipment used in HVM environments.”  


Thomas D. Jay
“Could you describe Multibeam's EBL Conceptual Design and Function?”

David K. Lam, P.h.D.
“Embodying four generations of development, Multibeam’s proprietary e-beam technology deploys a scalable multi-column array of miniature columns. Each column is controlled electrostatically with no magnetic field, and each is powered by a Schottky thermal field emitter.  Adjustable in beam energy from 5 to 50keV, each column contains a single beam; there is no beam splitting.  Multibeam’s unique architecture enables some 100 e-beam columns to be arrayed in a single module to print a 300mm wafer. Each mini-column is about the size of a marking pen and each array matches the size of a wafer. The columns in an array write independently and in parallel to achieve a throughput of 5 wafers per hour. 

Significantly, the absence of magnetic fields (and magnetic hysteresis) enables the e-beam in the column to be deflected at high speeds for blanking, positioning, shaping, and focusing. Multibeam optimizes its mini-columns at beam energies below 30keV, compared to other conventional EBDW systems running at 50-150keV.  Multibeam has developed companion technologies to further protect sensitive high-performance SoCs from any electron-induced damage while making the column array robust and lower-cost. 

Vector scanning by each individual beam is another crucial capability and key differentiation of the Multibeam approach. Multibeam’s vector-scanning technology enables each e-beam in the array to be individually deflected to where there is a pattern to write, efficiently skipping over wafer areas where there is no patterning required.”


Thomas D. Jay
“There is much debate surrounding EUV resist performance issues.  What unique concerns might there be for ebeam resist performance in a demanding nanometer scale HVM environment?”

David K. Lam, P.h.D.
“Multibeam’s e-beam technology uses commercial e-beam resists —including those that are currently used in mask writers. Widely available, these resists have been refined over three decades. In addition, carbon contamination can be cleaned with well-established techniques used in the Scanning Electron Microscope industry. EBDW does not involve tin, so there is no contamination associated with this metal as in EUV.”


Thomas D. Jay
“Have you any closing thoughts on Multibeam's confident market entry and future positioning?”

David K. Lam, P.h.D.
"Overcoming the wavelength limitations of optical lithography to produce ever smaller transistors is becoming very challenging. It’s no longer just a technical challenge…it is now a huge economic hurdle. While there is hope that EUV (soft X-ray) lithography will be the “next generation” disruptive solution, protracted delays in coming to market combined with EUV’s extraordinary high cost and a requirement for a vastly different infrastructure (e.g. new resists, new masks, etc) has opened the door for complementary solutions to play a cost-efficient role in reducing lithography costs.”

Dr. Lam comments that in addition to the technical challenges of EUV there are also economic challenges.  So to with eBeam. However, I believe there is a compelling case for the implementation of an EBL HVM strategy.  EBL will accelerate lithography enabling process evolution via Model Based Mask Data Prep (MB-MDP) along with other cost saving and process advantages to the HVM wafer fab.

I'd like to thank Dr. David Lam, Chairman, CEO, and Tom Rigoli, VP of Marketing at Multibeam Corporation for graciously responding to my inquiries, providing back ground information and insight on eBeam lithography and Multibeam.


Thomas D. Jay
Semiconductor Industry Consultant
Thomas.D.Jay@gmail.com
www.linkedin.com/
www.ThomasDaleJay.blogspot.com












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Acknowledgments

I'd like to thank the following semiconductor industry professionals and Lawrence Berkeley National Laboratory SEMI affiliates for responding to my research inquiries in preparing this article on eBeam lithography.    

David Lam, Ph.D.,  Founder of Lam Research, Chairman & CEO, Multibeam Corporation, Chairman, David Lam Group

Tom Rigoli, Vice President, Multibeam Corporation

Patrick Naulleau, Ph.D., Director, CXRO, Lawrence Berkeley National Laboratory

Kenneth Goldberg, Ph.D., Deputy Director, CXRO, Lawrence Berkeley National Laboratory

Chris Mack, Ph.D., Litho Guru, and Gentleman Scientist, (with F.M. Schellenberg, MEEF in Theory and Practice)

John Petersen, Principal, Periodic Structures/Petersen Advanced Lithography & SPIE Fellow

Referenced Presentations and Technical Papers

Yan Borodovsky, Ph.D., Director of Advanced Lithography, Senior Intel Fellow, Intel Corporation, The various paths to next-generation lithography, SPIE TV, You Tube 


Naoya Hayashi, Dai Nippon Printing Co., Ltd, Computational Lithography Requirements & Challenges for Mask Making

Repairing photomasks by nanomachining by Gregory McIntyre, Emily Gallaghar, Mark Lawliss, Tod Robinson, Michael Archuletta and Ron Bozak,  SPIE News Room

Anthony Adamov, D2S, Introduction to eMEEF, You Tube

Ryan Pearman, D2S, Discussion Computational Lithography, You Tube


  The Story Behind My Interview With Dr. David K. Lam

In preparing my May 15, 2013 blog article on electron beam lithography I contacted Tom Rigoli, Vice President at Multibeam Corporation to obtain background information on Dr. David K. Lam's strategic entry to the nanometer scale lithography market.  I forwarded a number of wide ranging questions for transmittal to Dr. Lam in order to establish a written question and answer interview format which might emulate the inquisitive depth of field of fellow semiconductor technologists, investors and intelligentsia.  Tom Rigoli returned Dr. Lam's written response, answering many of my questions along with applicable excerpts of previously published Multibeam marketing data.  After many hours of additional research on the web, and consultation with other recognized industry expertise, I condensed my original list of questions to bring focus to the key components of an important story.  During a later email exchange with Dr. Lam, he reviewed and clarified his written responses with additional commentary which comprises the “interview” appearing in my blog article.  The “interview” in its final form became an abbreviated but comprehensive summation of Multibeam's strategic initiative, marketing position, feature benefit review and forward looking observation of the semiconductor lithography market place.  While not a live spontaneous interview, it's an opportunity to gain Dr. Lam's measured insight and perspective of the electron beam lithography market and its challenges.