Unfortunately I was unable to attend the 2018 SPIE Advanced Lithography Conference but I continue to follow the subject of EUV Lithography with great interest. Having reviewed the many articles published after the conference, I have summarized my own thoughts and observations.
When I first entered the semiconductor market place, half micron CDs were the state of the art and the world anticipated the arrival of 0.2 micron geometries. Metrology mapping systems rapidly proliferated and provided visualization of critical resistivity, film thickness and lithography parametrics. Equally important, SPC (Statistical Process Control) enabled the effective management of complex multi-layer devices which became ever more challenging over time. Available metrology capabilities captured data collected from up to 625 sites (imagine) on a wafer’s process layer creating mountains of data for SPC analysis. I remember customer sites where process engineers crowded around metrology tools waiting for wafer maps to appear. Given the 286 microprocessor technology at the time, several agonizing minutes were required to compile and display wafer maps. Impatient process engineers were quickly rewarded with more rapid analysis as 386 and 486 microprocessors arrived. One day we were all stunned as a newly installed Pentium equipped work station displayed maps instantly with no wait time. Surplus processor speeds further advanced metrology by enabling statistical enhancement and stochastic analysis on the fly. With idle CPU time it became possible to dwell over a single test site, make multiple measurements and statistically treat the data enhancing accuracy and precision. Wafer maps comprised of such data yielded superior process control and set expectations for future device designs.
Fast forward to ten years ago. Enhancements in CPU speed and metrology went on to enable computational lithography. As it turns out, what you see is not always what you get from a mask design. Unanticipated effects can occur when mask design combined with local physical effects yield distorted images when printed on a wafer. In these instances lithography tool characteristics and mask metrology data can be utilized to compute an optical correction for the mask. Computational lithography can yield an altered mask structure which appears malformed but prints the intended image when corrected for distorting influences.
The benefits of computational lithography are best obtained in a data rich environment; tool data obtained from focus exposure plots, TIS data, physical interactions of materials and other well understood process variables. The current challenge posed by EUVL is the absence of information required for analysis. Even with advanced computer algorithms smoothing stochastic/random data a sufficiently accurate distribution of process/event related phenomenon are not available in the absence of a photon rich environment. EUV photon densities which can be counted on one hand yield process uncertainties you can drive a Mack truck through (I hear this is being worked on). These observations have been discussed extensively at prior conferences; CD uniformity, LER (Line Edge Roughness) often thought to be primarily dosimetry related can be caused by other influential factors. Having studied many conference materials published by the eBeam Initiative, it seemed advanced ebeam shot tasking algorithms provided the best pattern generation abilities, providing precise control of beam energy/current, dwell time over target and beam spot size. In spite of precise control of these critical variables, ebeam lithography can still benefit from computational lithography analysis.
It would seem the 2018 SPIE conference has brought us full circle, resuming prior discussions on available EUV source power and compensation for its absence. We are again discussing resist materials for use with less than optimal EUV power; their sensitivities to secondary emissions and related cause/effect variables. It would seem we must pursue three strategies in the continued quest for EUVL.
1. QAM (Quantum Assisted Metrology). The number of structures resulting from 5 nm design rules in High Volume Manufacturing continue to grow geometrically. Given fifty or more mask levels it will be challenging to fabricate trillions of critical device structures, all of which must be perfectly formed to achieve anticipated process yields. The lithography challenge here remains significant as it is reported that EUV masks are not yet interchangeable among EUV steppers. The metrology required for analysis and SPC of such devices is currently insufficient to the task as any measurement speed improvements are offset by the sheer volume of CDs to be measured. QAM (Quantum Assisted Metrology) providing parallel processing of data distributed among multiple logic states would seem to be a priority pursuit in extending the viability of EUVL.
2. QA-IMF (Quantum Assisted - In-situ Metrology Fabrication). Assuming the successful implementation of QAM, a future EUVL strategy might entail a QAM module providing real time feedback of metrology/process control information to QA-IMF (Quantum Assisted - In-situ Metrology Fabrication tools). Metrology data fed back to optimize fabrication/lithography tool accuracy is not a new concept but when considered for use with EUVL on 5 nm structures we must similarly consider the implementation of Quantum computed data to make the concept viable. E beam systems are being proposed featuring In-situ metrology providing feed back to enhance write accuracy. Similarly implemented in EUVL, such systems could benefit from this design approach and greatly improve speed, accuracy and precision for advanced maufacturing.
3. Continued development of a high power/uptime EUV light source. I will not elaborate here other than to say we are all aware we will need an abundance of EUV photons to adequately address future EUVL requirements.
When I first entered the semiconductor market place, half micron CDs were the state of the art and the world anticipated the arrival of 0.2 micron geometries. Metrology mapping systems rapidly proliferated and provided visualization of critical resistivity, film thickness and lithography parametrics. Equally important, SPC (Statistical Process Control) enabled the effective management of complex multi-layer devices which became ever more challenging over time. Available metrology capabilities captured data collected from up to 625 sites (imagine) on a wafer’s process layer creating mountains of data for SPC analysis. I remember customer sites where process engineers crowded around metrology tools waiting for wafer maps to appear. Given the 286 microprocessor technology at the time, several agonizing minutes were required to compile and display wafer maps. Impatient process engineers were quickly rewarded with more rapid analysis as 386 and 486 microprocessors arrived. One day we were all stunned as a newly installed Pentium equipped work station displayed maps instantly with no wait time. Surplus processor speeds further advanced metrology by enabling statistical enhancement and stochastic analysis on the fly. With idle CPU time it became possible to dwell over a single test site, make multiple measurements and statistically treat the data enhancing accuracy and precision. Wafer maps comprised of such data yielded superior process control and set expectations for future device designs.
Fast forward to ten years ago. Enhancements in CPU speed and metrology went on to enable computational lithography. As it turns out, what you see is not always what you get from a mask design. Unanticipated effects can occur when mask design combined with local physical effects yield distorted images when printed on a wafer. In these instances lithography tool characteristics and mask metrology data can be utilized to compute an optical correction for the mask. Computational lithography can yield an altered mask structure which appears malformed but prints the intended image when corrected for distorting influences.
The benefits of computational lithography are best obtained in a data rich environment; tool data obtained from focus exposure plots, TIS data, physical interactions of materials and other well understood process variables. The current challenge posed by EUVL is the absence of information required for analysis. Even with advanced computer algorithms smoothing stochastic/random data a sufficiently accurate distribution of process/event related phenomenon are not available in the absence of a photon rich environment. EUV photon densities which can be counted on one hand yield process uncertainties you can drive a Mack truck through (I hear this is being worked on). These observations have been discussed extensively at prior conferences; CD uniformity, LER (Line Edge Roughness) often thought to be primarily dosimetry related can be caused by other influential factors. Having studied many conference materials published by the eBeam Initiative, it seemed advanced ebeam shot tasking algorithms provided the best pattern generation abilities, providing precise control of beam energy/current, dwell time over target and beam spot size. In spite of precise control of these critical variables, ebeam lithography can still benefit from computational lithography analysis.
Full Circle With Line Edge Roughness
It would seem the 2018 SPIE conference has brought us full circle, resuming prior discussions on available EUV source power and compensation for its absence. We are again discussing resist materials for use with less than optimal EUV power; their sensitivities to secondary emissions and related cause/effect variables. It would seem we must pursue three strategies in the continued quest for EUVL.
1. QAM (Quantum Assisted Metrology). The number of structures resulting from 5 nm design rules in High Volume Manufacturing continue to grow geometrically. Given fifty or more mask levels it will be challenging to fabricate trillions of critical device structures, all of which must be perfectly formed to achieve anticipated process yields. The lithography challenge here remains significant as it is reported that EUV masks are not yet interchangeable among EUV steppers. The metrology required for analysis and SPC of such devices is currently insufficient to the task as any measurement speed improvements are offset by the sheer volume of CDs to be measured. QAM (Quantum Assisted Metrology) providing parallel processing of data distributed among multiple logic states would seem to be a priority pursuit in extending the viability of EUVL.
2. QA-IMF (Quantum Assisted - In-situ Metrology Fabrication). Assuming the successful implementation of QAM, a future EUVL strategy might entail a QAM module providing real time feedback of metrology/process control information to QA-IMF (Quantum Assisted - In-situ Metrology Fabrication tools). Metrology data fed back to optimize fabrication/lithography tool accuracy is not a new concept but when considered for use with EUVL on 5 nm structures we must similarly consider the implementation of Quantum computed data to make the concept viable. E beam systems are being proposed featuring In-situ metrology providing feed back to enhance write accuracy. Similarly implemented in EUVL, such systems could benefit from this design approach and greatly improve speed, accuracy and precision for advanced maufacturing.
3. Continued development of a high power/uptime EUV light source. I will not elaborate here other than to say we are all aware we will need an abundance of EUV photons to adequately address future EUVL requirements.
In conclusion, I continue to follow the EUV program and the contributions of many with great interest. It would seem the application of quantum computing might provide the best approach to any demanding semiconductor problem set inclusive of EUVL. [1] IBM seems a likely candidate to assist in providing an accelerated path adapting quantum computation to semiconductor applications.
We will see what the future brings.
Regards to all,
We will see what the future brings.
Regards to all,
Thomas D. Jay
Semiconductor Industry Consultant
Thomas.Dale.Jay@gmail.com
https://ThomasDaleJay.blogspot.com
Thomas D. Jay YouTube Channel
Thomas D. Jay is a member of SPIE and IEEE
Corporate, private entities or publications referenced or linked in this article are the respective owners of their logos, trademarks, service marks, media content and intellectual property. Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. Thomas D. Jay is not a registered financial advisor. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated. Thomas D. Jay does not agree to indemnify or hold harmless vendors, clients or third parties to related contractual agreements and reserves the right to applicable legal remedies in lieu of arbitration. These terms are subject to change. Concerned parties should check this blog site for periodic updates.
References and acknowledgements:
[1] IBM web site
https://youtu.be/yy6TV9Dntlw
Semiconductor Industry Consultant
Thomas.Dale.Jay@gmail.com
https://ThomasDaleJay.blogspot.com
Thomas D. Jay YouTube Channel
Thomas D. Jay is a member of SPIE and IEEE
Corporate, private entities or publications referenced or linked in this article are the respective owners of their logos, trademarks, service marks, media content and intellectual property. Unless otherwise disclosed, Thomas D. Jay has no financial interest in companies referenced in blog articles or other published media communications. Thomas D. Jay is not a registered financial advisor. No representation is made to either buy or sell securities. Opinions expressed by Thomas D. Jay are his own. Thomas D. Jay does not employ or otherwise utilize/authorize third party agents to express his opinions, represent his interests or conduct business on his behalf except where formally contractually designated. Thomas D. Jay does not agree to indemnify or hold harmless vendors, clients or third parties to related contractual agreements and reserves the right to applicable legal remedies in lieu of arbitration. These terms are subject to change. Concerned parties should check this blog site for periodic updates.
References and acknowledgements:
[1] IBM web site
https://youtu.be/yy6TV9Dntlw
